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| 1 for more information www.linear.com/LTC5599 typical a pplica t ion fea t ures descrip t ion 30mhz to 1300mhz low power direct quadrature modulator a pplica t ions l, lt , lt c , lt m , linear technology, and the linear logo are registered trademarks and quikeval is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. the lt c ? 5599 is a direct conversion i/q modulator de- signed for low power wireless applications that enable direct modulation of differential baseband i and q signals on an rf carrier. single side- band modulation or side- band suppressed upconversion can be achieved by applying 90 phase-shifted signals to the i and q inputs. the i/q baseband input ports can be either ac or dc coupled to a source with a common mode voltage level of about 1.4v. the spi interface controls the supply current, modulator gain, and allows optimization of the lo carrier feedthrough and side-band suppression, with sine wave or square wave lo drive. a fixed lc network on the lo and rf ports covers a continuous 90 mhz to 1300 mhz operation. an on-chip thermometer can be activated to compensate for gain-temperature variations. more accurate temperature measurements can be made using an on-chip diode. in addition, a continuous analog gain control (v ctrl ) pin can be used for fast power control. 90mhz to 1300mhz direct conversion transmitter application n frequency range: 30mhz to 1300mhz n low power: 2.7v to 3.6v supply; 28ma n low lo carrier leakage: C51.5dbm at 500mhz n side-band suppression: C52.6dbc at 500mhz n output ip3: 20.8dbm at 500mhz n low rf output noise floor: C156dbm/hz at 6mhz offset, p rf = 3dbm n sine wave or square wave lo drive n spi control: adjustable gain: C19db to 0db in 1db steps effecting supply current from 8ma to 35ma i/q offset adjust: C65dbm lo carrier leakage i/q gain/ phase adjust: C60 dbc side - band suppressed n 24-lead qfn 4mm 4mm package n wireless microphones n battery powered radios n ad-hoc wireless infrastructure networks n white-space transmitters n software defined radios (sdr) n military radios evm and noise floor vs rf output power and digital gain setting with 1ms/s 16-qam signal LTC5599 v cc 3.3v 5599 ta01a 1nf + 4.7f 90 0 i-channel q-channel thermometer ttck spi baseband generator en rf = 90mhz to 1300mhz pa vco/synthesizer 10nf v ctrl i-dac q-dac v i v i rf output power (dbm) ?15 rms evm (%) 10 9 7 5 8 6 4 3 0 1 ?105 ?115 ?125 ?135 ?145 ?155 ?165 2 0 5599 ta01b 5 ?5 ?10 dg = ?19 dg = ?16 dg = ?12 dg = ?8 dg = ?4 dg = 0 ltc 5599 5599f 39nh 15pf
2 for more information www.linear.com/LTC5599 p in c on f igura t ion a bsolu t e maxi m u m r a t ings (note 1) 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 25 2 1 13 14 15 16 17 18 v ctrl gnd lol loc gnd ttck gndrf gndrf rf gndrf gndrf gndrf v cc en sdo sdi sclk csb temp bbpi bbmi bbpq bbmq gnd gnd t jmax = 150c, ja = 43c/w, jc = 4.5c/w (at exposed pad ) exposed pad (pin 25) is gnd, must be soldered to pcb o r d er i n f or m a t ion supply voltage ......................................................... 3.8 v com mon mode level of bbpi , bbmi , and bbpq , bbmq ........................................................ 2v lol , loc dc voltage ............................................. 0.1 v lo l , loc input power ( note 15) .......................... 20 dbm cu rrent sink of temp , sdo .................................... 10 ma volt age on any pin ( note 16) ........... C0.3 v to v cc + 0.3 v t jmax .................................................................... 150 c ca se operating temperature range ........C40 c to 105 c storage temperature range .................. C65 c to 150 c lead free finish tape and reel part marking package description case temperature range LTC5599iuf#pbf LTC5599iuf#trpbf 5599 24-lead (4mm 4mm) plastic qfn C40c to 105c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ please refer to: http://www.linear.com/designtools/packaging/ for the most recent package drawings. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25 c. v cc = 3.3 v, en = 3.3 v, v ctrl = 3.3 v, p lo = 0dbm, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p(diff, i or q) , i and q 90 shifted, lower sideband selection, all registers set to default values, unless otherwise noted. test circuit is shown in figure 13. symbol parameter conditions min typ max units f lo = 150mhz, f rf1 = 147.9mhz, f rf2 = 148mhz, register 0x00 = 0x62 s 22(on) rf port return loss C26 db f lo(match) lo match frequency range s11 < C10db 116 to 272 mhz gain conversion voltage gain 20 ? log (v rf(out)(50) /v in(diff)(i or q) ) C7.5 db p out absolute output power 1v p-p(diff) cw signal, i and q C3.5 dbm op1db output 1db compression 5 dbm oip2 output 2nd order intercept (note 5) 70.5 dbm oip3 output 3rd order intercept (note 6) 21.7 dbm nfloor rf output noise floor no baseband ac input signal (note 3) C155.3 dbm/hz sb side-band suppression (note 7) C61.4 dbc loft carrier leakage (lo feedthrough) (note 7) en = low (note 7) C52.8 C84.8 dbm dbm 2loft lo feedthrough at 2xlo C59 dbm ltc 5599 5599f 3 for more information www.linear.com/LTC5599 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25 c. v cc = 3.3 v, en = 3.3 v, v ctrl = 3.3 v, p lo = 0dbm, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p(diff, i or q) , i and q 90 shifted, lower sideband selection, all registers set to default values, unless otherwise noted. test circuit is shown in figure 13. symbol parameter conditions min typ max units 2lo signal powers at 2xlo maximum of 2 f lo C 2f bb ; 2f lo C f bb ; 2f lo + f bb , 2f lo + 2f bb C51 dbc 3loft lo feedthrough at 3xlo C57 dbm 3lo signal powers at 3xlo maximum of 3f lo C f bb ; 3f lo + f bb C10.7 dbc bw1db bb C1db baseband bandwidth r source = 50, differential 15 mhz bw3db bb C3db baseband bandwidth r source = 50, differential 28 mhz f lo = 500mhz, f rf1 = 497.9mhz, f rf2 = 498mhz, register 0x00 = 0x2d s 22(on) rf port return loss C26 db f lo(match) lo match frequency range s11 < C10db 180 to 1900 mhz gain conversion voltage gain 20 ? log (v rf(out)(50) /v in(diff)(i or q) ) C7.7 db p out absolute output power 1v p-p(diff) cw signal, i and q C3.7 dbm op1db output 1db compression 5.0 dbm oip2 output 2nd order intercept (note 5) 63.6 dbm oip3 output 3rd order intercept (note 6) 20.8 dbm nfloor rf output noise floor no baseband ac input signal (note 3) p out = 3dbm (note 3) C156.7 C 156.0 dbm/hz dbm/hz sb side-band suppression (note 7) C52.6 dbc loft carrier leakage (lo feedthrough) (note 7) en = low (note 7) C51.5 C67.5 dbm dbm 2loft lo feedthrough at 2xlo C61 dbm 2lo signal powers at 2xlo maximum of 2 f lo C 2f bb ; 2f lo C f bb ; 2f lo + f bb , 2f lo + 2f bb C51 dbc 3loft lo feedthrough at 3xlo C62 dbm 3lo signal powers at 3xlo maximum of 3f lo C f bb ; 3f lo + f bb C11.8 dbc bw1db bb C1db baseband bandwidth r source = 50, differential 29 mhz bw3db bb C3db baseband bandwidth r source = 50, differential 57 mhz f lo = 900mhz, f rf1 = 897.9mhz, f rf2 = 898mhz, register 0x00 = 0x12 s 22(on) rf port return loss C28 db f lo(match) lo match frequency range s11 < C10db 223 to 1902 mhz gain conversion voltage gain 20 ? log (v rf(out)(50) /v in(diff)(i or q) ) C8.9 db p out absolute output power 1v p-p(diff) cw signal, i and q C4.9 dbm op1db output 1db compression 4.1 dbm oip2 output 2nd order intercept (note 5) 63.5 dbm oip3 output 3rd order intercept (note 6) 18.4 dbm nfloor rf output noise floor no baseband ac input signal (note 3) C155.6 dbm/hz sb side-band suppression (note 7) C61.3 dbc loft carrier leakage (lo feedthrough) (note 7) en = low (note 7) C58.6 C62.3 dbm dbm 2loft lo feedthrough at 2xlo C59 dbm 2lo signal powers at 2xlo maximum of 2 f lo C 2f bb ; 2f lo C f bb ; 2f lo + f bb , 2f lo + 2f bb C51 dbc ltc 5599 5599f 4 for more information www.linear.com/LTC5599 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25 c. v cc = 3.3 v, en = 3.3 v, v ctrl = 3.3 v, p lo = 0dbm, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p(diff, i or q) , i and q 90 shifted, lower sideband selection, all registers set to default values, unless otherwise noted. test circuit is shown in figure 13. e lec t rical c harac t eris t ics symbol parameter conditions min typ max units 3loft lo feedthrough at 3xlo C60 dbm 3lo signal powers at 3xlo maximum of 3f lo C f bb ; 3f lo + f bb C19.2 dbc bw1db bb C1db baseband bandwidth r source = 50, differential 37 mhz bw3db bb C3db baseband bandwidth r source = 50, differential 69 mhz variable gain control (v ctrl ) v ctrl r gain control voltage range set bit 6 in register 0x01 0.9 to 3.3 v t ctrl gain control response time set bit 6 in register 0x01 (note 8) 20 ns z ctrl gain control input impedance set bit 6 in register 0x01 10 pf i ctrl dc input current set bit 6 in register 0x01 clear bit 6 in register 0x01 2.58 0 ma ma baseband inputs (bbpi, bbmi, bbpq, bbmq) v cmbb dc common mode voltage internally generated 1.42 v r in(diff) input resistance differential 1.8 k r in(cm) common mode input resistance four baseband pins shorted 350 i bb(off) baseband leakage current four baseband pins shorted, en = low 1.3 na v swing amplitude swing no hard clipping, single-ended, digital gain (dg) = C10 1.2 v p-p power supply (v cc ) v cc supply voltage 2.7 3.3 3.6 v v ret(min) minimum data retention voltage (note 14) 1.6 1.3 v i cc(on) supply current en = high 20 28 37 ma i cc(range) supply current range en = high, register 0x01 from 0x00 to 0x13 8 to 36 ma i cc(off) supply current, sleep mode en = 0v 0.7 9 a t on turn-on time en = low to high (notes 8, 12) 167 ns t off turn-off time en = high to low (notes 9, 12) 53 ns t sb side-band suppression settling register 0x00 change, 6 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics output ip3 vs rf frequency and digital gain setting side-band suppression vs rf frequency and digital gain setting supply current vs supply voltage supply current vs digital gain setting gain vs rf frequency and digital gain setting output ip2 vs rf frequency and digital gain setting lo leakage vs rf frequency and digital gain setting v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. side-band suppression vs lo frequency for gain tempcomp off side-band suppression vs lo frequency for gain tempcomp on lo frequency (mhz) 50 side-band suppression (dbc) ?30 ?60 ?50 ?40 ?70 1250 250 650 850 1050 5599 g09 450 3.3v, 25c 2.7v, 25c 3.3v, 105c 3.3v, ?40c 3.6v, 25c 3.3v, 85c 3.3v, ?10c supply voltage (v) 2.7 supply current (ma) 36 34 32 28 24 30 26 22 20 5599 g01 3.6 3 3.3 ?40c ?10c 25c 85c 105c digital gain setting ?19 ?17 ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 supply current (ma) 40 30 20 10 0 5599 g02 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c rf frequency (mhz) 50 250 450 650 850 1050 1250 gain (db) 0 ?5 ?20 ?25 ?10 ?15 ?30 5599 g03 digital gain setting (dg) = 0 (register 0x01 = 0x00) digital gain setting (dg) = ?19 (register 0x01 = 0x13) rf frequency (mhz) 50 oip3 (dbm) 20 15 5 10 0 5599 g04 1250 250 650 850 1050 450 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 oip2 (dbm) 80 70 50 60 40 5599 g05 1250 250 650 850 1050 450 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 lo leakage (dbm) ?40 ?50 ?70 ?60 ?80 1250 250 650 850 1050 5599 g06 450 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 side-band suppression (dbc) ?10 ?20 ?50 ?60 ?40 ?30 ?70 1250 250 650 850 1050 5599 g07 450 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 lo frequency (mhz) 50 side-band suppression (dbc) ?30 ?60 ?50 ?40 ?70 1250 250 650 850 1050 5599 g08 450 tempupdt = 1 3.3v, 25c 2.7v, 25c 3.3v, 105c 3.3v, ?40c 3.6v, 25c 3.3v, 85c 3.3v, ?10c ltc 5599 5599f 7 for more information www.linear.com/LTC5599 v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. noise floor vs rf frequency and digital gain setting output 1db compression point vs rf frequency and digital gain setting and 3.3v supply output 1db compression point vs rf frequency and digital gain setting at 85c output 1db compression point vs rf frequency and digital gain setting at 105c output 1db compression point vs rf frequency and digital gain setting at C10c output 1db compression point vs rf frequency and digital gain setting and 2.7v supply typical p er f or m ance c harac t eris t ics gain vs rf frequency and v ctrl output 1db compression point vs rf frequency and digital gain setting at C40c output 1db compression point vs rf frequency and digital gain setting and 3.6v supply rf frequency (mhz) 50 250 450 650 850 1050 1250 rf noise floor (dbm/hz) ?140 ?145 ?160 ?165 ?150 ?155 ?170 5599 g10 digital gain setting = 0 (register 0x01 = 0x00) digital gain setting = ?19 (register 0x01 = 0x13) rf frequency (mhz) 50 250 450 650 850 1050 1250 op1db (dbm) 6 ?2 ?6 2 ?10 5599 g11 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 250 450 650 850 1050 1250 op1db (dbm) 6 ?2 ?6 2 ?10 5599 g12 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 250 450 650 850 1050 1250 op1db (dbm) 6 ?2 ?6 2 ?10 5599 g16 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 250 450 650 850 1050 1250 op1db (dbm) 6 ?2 ?6 2 ?10 5599 g17 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 250 450 650 850 1050 1250 gain (db) 0 ?40 ?60 ?80 ?20 ?100 5599 g18 agctrl = 1 3.3v 1.35v 1v 1.8v 1.6v 1.45v 1.25v 1.15v rf frequency (mhz) 50 250 450 650 850 1050 1250 op1db (dbm) 6 ?2 ?6 2 ?10 5599 g13 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 250 450 650 850 1050 1250 op1db (dbm) 6 ?2 ?6 2 ?10 5599 g14 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 rf frequency (mhz) 50 250 450 650 850 1050 1250 op1db (dbm) 6 ?2 ?6 2 ?10 5599 g15 dg 0 dg ?1 dg ?2 dg ?3 dg ?4 dg ?5 dg ?6 dg ?7 dg ?8 dg ?9 dg ?10 dg ?11 dg ?12 dg ?13 dg ?14 dg ?15 dg ?16 dg ?17 dg ?18 dg ?19 ltc 5599 5599f 8 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics gain vs rf frequency for 30mhz lo match output ip3 vs rf frequency for 30mhz lo match noise floor vs v ctrl gain noise floor vs rf frequency noise floor vs rf power noise floor vs rf frequency and v ctrl input ip3 vs rf frequency and v ctrl input ip2 vs rf frequency and v ctrl side-band suppression vs rf frequency for 30mhz lo match v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. rf frequency (mhz) 50 250 450 650 850 1050 1250 iip3 (dbm) 40 20 10 30 0 5599 g19 agctrl = 1 1.35v 1v 1.8v 1.6v 1.45v 1.25v 1.15v 3.3v rf frequency (mhz) 50 rf noise floor (dbm/hz) ?150 ?154 ?162 ?158 ?166 1250 250 650 850 1050 5599 g21 450 3.3v 2v 1.9v 1.85v 1.8v 1.75 1.65 1.6v 1.55v 1.5v 1.45v 1.4v 1.3v 1v rf frequency (mhz) 50 rf noise floor (dbm/hz) ?140 ?144 ?152 ?156 ?148 ?160 1250 250 650 850 1050 5599 g22 450 3.3v, 25c 3.6v, 25c 2.7v, 25c 3.3v, 85c 3.3v, 105c 3.3v, ?10c 3.3v, ?40c rf power (dbm) ?10 rf noise floor (dbm/hz) ?152 ?154 ?158 ?160 ?162 ?156 ?164 6 ?8 ?4 ?2 2 4 0 5599 g23 ?6 dg = 0 dg = ?4 dg = ?8 dg = ?12 dg = ?16 dg = ?19 v ctrl gain (db) ?80 rf noise floor (dbm/hz) ?150 ?154 ?162 ?158 ?166 ?10 ?70 ?50 ?40 ?20 ?30 5599 g24 ?60 agctrl = 1 3.3v, 25c 3.6v, 25c 2.7v, 25c 3.3v, 85c 3.3v, 105c 3.3v, ?10c 3.3v, ?40c rf frequency (mhz) 20 gain (db) ?5 ?6 ?7 ?8 ?9 ?10 ?11 ?12 ?13 ?14 ?15 50 25 35 40 45 5599 g25 30 3.3v, 25c 3.3v, 105c 3.3v, ?40c 3.3v, 0c 3.3v, 85c 3.3v, ?10c 3.3v, 55c rf frequency (mhz) 50 250 450 650 850 1050 1250 iip2 (dbm) 80 60 50 40 30 20 70 10 5599 g20 agctrl = 1 1v 1.8v 1.6v 1.45v 1.25v 1.15v 3.3v 1.35v rf frequency (mhz) 20 oip3 (dbm) 21 20 19 18 17 16 15 50 25 35 40 45 5599 g26 30 3.3v, 25c 3.3v, 105c 3.3v, ?40c 3.3v, 0c 3.3v, 85c 3.3v, ?10c 3.3v, 55c rf frequency (mhz) 20 side-band suppression (dbc) ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 50 25 30 40 45 5599 g27 35 3.3v, 85c 3.3v, ?10c 3.3v, 55c 3.3v, 25c 3.3v, 105c 3.3v, ?40c 3.3v, 0c ltc 5599 5599f 9 for more information www.linear.com/LTC5599 gain vs rf frequency for 70mhz lo match typical p er f or m ance c harac t eris t ics output ip3 vs rf frequency for 70mhz lo match gain vs lo power at f lo = 150mhz gain vs lo power at f lo = 500mhz output ip3 vs lo power at f lo = 150mhz gain vs lo power at f lo = 1260mhz output ip3 vs lo power at f lo = 500mhz gain vs lo power at f lo = 900mhz side-band suppression vs rf frequency for 70mhz lo match v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. rf frequency (mhz) 50 side-band suppression (dbc) ?10 ?20 ?30 ?40 ?50 ?60 ?70 120 60 70 100 110 5599 g30 80 90 3.3v, 25c 3.3v, 105c 3.3v, ?40c 3.3v, 0c 3.3v, 85c 3.3v, ?10c 3.3v, 55c lo power (dbm) ?10 gain (db) ?6 ?10 ?14 ?18 ?22 2 4 6 ?8 ?6 ?2 0 5599 g31 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 gain (db) ?6 ?10 ?14 ?18 ?22 2 4 6 ?8 ?6 ?2 0 5599 g32 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 gain (db) ?6 ?10 ?14 ?18 ?22 2 4 6 ?8 ?6 ?2 0 5599 g33 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 gain (db) ?6 ?10 ?14 ?18 ?22 2 4 6 ?8 ?6 ?2 0 5599 g34 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 oip3 (dbm) 23 19 15 11 7 2 4 6 ?8 ?6 ?2 0 5599 g35 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 oip3 (dbm) 23 19 15 11 7 2 4 6 ?8 ?6 ?2 0 5599 g36 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c rf frequency (mhz) 50 gain (db) ?5 ?6 ?7 ?8 ?9 ?10 120 60 70 90 100 110 5599 g28 80 3.3v, 25c 3.3v, 105c 3.3v, ?40c 3.3v, 0c 3.3v, 85c 3.3v, ?10c 3.3v, 55c rf frequency (mhz) 50 oip3 (dbm) 23 22 21 20 19 18 120 60 70 90 100 110 5599 g29 80 3.3v, 25c 3.3v, 105c 3.3v, ?40c 3.3v, 0c 3.3v, 85c 3.3v, ?10c 3.3v, 55c ltc 5599 5599f 10 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics output ip2 vs lo power at f lo = 900mhz output ip2 vs lo power at f lo = 500mhz lo leakage vs lo power at f lo = 900mhz lo leakage vs lo power at f lo = 500mhz lo leakage vs lo power at f lo = 150mhz output ip2 vs lo power at f lo = 1260mhz output ip2 vs lo power at f lo = 150mhz output ip3 vs lo power at f lo = 900mhz output ip3 vs lo power at f lo = 1260mhz v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. lo power (dbm) ?10 oip3 (dbm) 20 16 12 8 4 0 2 4 6 ?8 ?6 ?2 0 5599 g38 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 oip2 (dbm) 75 70 65 60 55 50 45 40 2 4 6 ?8 ?6 ?2 0 5599 g39 ?4 3.3v 3.6v 2.7v 85c 105c ?10c ?40c digital gain = ?4 (solid) digital gain = ?10 (dashed) lo power (dbm) ?10 oip2 (dbm) 75 70 65 60 55 40 50 45 2 4 6 ?8 ?6 ?2 0 5599 g40 ?4 digital gain = ?4 (solid) digital gain = ?10 (dashed) 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 oip2 (dbm) 75 70 65 60 55 40 50 45 2 4 6 ?8 ?6 ?2 0 5599 g41 ?4 digital gain = ?4 (solid) digital gain = ?10 (dashed) 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 oip2 (dbm) 75 70 65 60 55 40 50 45 2 4 6 ?8 ?6 ?2 0 5599 g42 ?4 digital gain = ?4 (solid) digital gain = ?10 (dashed) 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 lo leakage (dbm) ?45 ?50 ?55 ?60 2 4 6 ?8 ?6 ?2 0 5599 g44 ?4 3.3v 3.6v 2.7v 85c 105c ?10c ?40c digital gain = ?4 digital gain = ?10 lo power (dbm) ?10 lo leakage (dbm) ?45 ?50 ?55 ?60 ?65 ?70 2 4 6 ?8 ?6 ?2 0 5599 g45 ?4 3.3v 3.6v 2.7v 85c 105c ?10c ?40c digital gain = ?4 digital gain = ?10 lo power (dbm) ?10 oip3 (dbm) 23 19 15 11 7 2 4 6 ?8 ?6 ?2 0 5599 g37 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 lo leakage (dbm) ?45 ?50 ?55 ?60 ?65 2 4 6 ?8 ?6 ?2 0 5599 g43 ?4 digital gain = ?4 digital gain = ?10 3.3v 3.6v 2.7v 85c 105c ?10c ?40c ltc 5599 5599f 11 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics side-band suppression vs lo power at f lo = 150mhz lo leakage vs lo power at f lo = 1260mhz side-band suppression vs lo power at f lo = 1260mhz side-band suppression vs lo power at f lo = 900mhz output ip3 vs v ctrl gain v ctrl current vs v ctrl voltage gain vs v ctrl voltage supply current vs v ctrl voltage side-band suppression vs lo power at f lo = 500mhz v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. lo power (dbm) ?10 lo leakage (dbm) ?44 ?48 ?56 ?52 ?60 ?64 ?72 ?76 ?68 ?80 2 4 6 ?8 ?6 ?2 0 5599 g46 ?4 3.3v 3.6v 2.7v 85c 105c ?10c ?40c digital gain = ?4 digital gain = ?10 lo power (dbm) ?10 side-band suppression (dbc) ?40 ?45 ?50 ?65 ?55 ?60 2 4 6 ?8 ?6 ?2 0 5599 g47 ?4 digital gain = ?4 (solid) digital gain = ?10 (dashed) 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 side-band suppression (dbc) ?40 ?45 ?50 ?65 ?55 ?60 2 4 6 ?8 ?6 ?2 0 5599 g48 ?4 digital gain = ?4 (solid) digital gain = ?10 (dashed) 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 side-band suppression (dbc) ?40 ?45 ?50 ?65 ?55 ?60 2 4 6 ?8 ?6 ?2 0 5599 g49 ?4 digital gain = ?4 (solid) digital gain = ?10 (dashed) 3.3v 3.6v 2.7v 85c 105c ?10c ?40c lo power (dbm) ?10 side-band suppression (dbc) ?40 ?42 ?41 ?44 ?43 ?50 ?46 ?45 ?48 ?47 ?49 2 4 6 ?8 ?6 ?2 0 5599 g50 ?4 digital gain = ?4 (solid) digital gain = ?10 (dashed) 3.3v 3.6v 2.7v 85c 105c ?10c ?40c v ctrl (v) 0.9 i ctrl (ma) 3.0 2.5 1.5 2.0 2.7 3 3.3 1.2 1.5 2.1 2.4 5599 g52 1.8 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c 3.3v, ?10c 3.3v, 105c v ctrl voltage (v) 0.9 gain (db) 0 ?20 ?80 ?40 ?60 2.7 3 3.3 1.2 1.5 2.1 2.4 5599 g53 1.8 agctrl = 1 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c 3.3v, ?10c 3.3v, 105c gain set by v ctrl (db) ?27 oip3 (dbm) 25 20 ?10 15 10 5 0 ?5 ?11 ?7 ?23 ?15 5599 g54 ?19 agctrl = 1 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c 3.3v, ?10c 3.3v, 105c v ctrl voltage (v) 0.9 supply current (ma) 40 30 0 20 10 2.7 3 3.3 1.2 1.5 2.1 2.4 5599 g51 1.8 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c 3.3v, ?10c 3.3v, 105c agctrl = 1 ltc 5599 5599f 12 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics output ip3 vs baseband amplitude p rf , im2, im3 vs baseband amplitude gain minus digital gain vs digital gain setting gain vs digital gain setting lo leakage vs lo frequency for gain tempcomp off output ip2 vs baseband amplitude side-band suppression vs v ctrl gain output ip2 vs v ctrl gain lo leakage vs v ctrl gain v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. gain set by v ctrl (db) ?17 oip2 (dbm) 70 65 60 55 50 45 40 ?9 ?7 ?15 ?11 5599 g55 ?13 agctrl = 1 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c 3.3v, ?10c 3.3v, 105c gain set by v ctrl (db) ?77 lo leakage (dbm) ?30 ?40 ?50 ?60 ?70 ?80 ?17 ?7 ?67 ?57 ?27 5599 g56 ?37 ?47 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c 3.3v, ?10c 3.3v, 105c agctrl = 1 gain set by v ctrl (db) ?77 side-band suppression (dbc) ?20 ?25 ?30 ?35 ?40 ?50 ?45 ?55 ?60 ?17 ?7 ?67 ?57 ?27 5599 g57 ?37 ?47 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c 3.3v, ?10c 3.3v, 105c agctrl = 1 digital gain setting ?19 gain (db) ?5 ?9 ?13 ?17 ?21 ?25 ?3 ?11 ?15 5599 g58 ?7 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c agctrl = 1 baseband amplitude (v peak(diff) ) 0.1 p rf per tone (dbm), im2, im3 (dbc) 10 ?10 ?30 ?50 ?70 ?90 5599 g60 1 p rf for dg = 0, ?4, ?8, ?12, ?16, ?19, im2 for dg = 0, ?4, ?8, ?19, ?12, ?16 im3 for dg = 0, ?19, ?16, ?4, ?12, ?8 baseband amplitude (v peak(diff) ) 0.1 oip3 (dbm) 20 15 10 5 0 ?5 5599 g61 1 dg = 0 dg = ?8 dg = ?16 dg = ?4 dg = ?12 dg = ?19 baseband amplitude (v peak(diff) ) 0.1 oip2 (dbm) 70 60 50 40 30 5599 g62 1 dg = 0 dg = ?8 dg = ?16 dg = ?4 dg = ?12 dg = ?19 lo frequency (mhz) 50 lo leakage (dbm) ?40 ?45 ?50 ?55 ?60 ?65 ?70 1050 1250 450 250 850 5599 g63 650 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, 105c tempupdt = 1 3.3v, ?10c 3.3v, ?40c digital gain setting ?19 gain ? digital gain (db) ?2 ?3 ?4 ?5 ?6 ?3 ?11 ?15 5599 g59 ?7 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, ?40c ltc 5599 5599f 13 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics lo leakage vs lo frequency and digital gain setting after calibration at dg = C4 side-band suppression vs lo frequency and digital gain setting after calibration at dg = C4 worst - case side- band suppression over five parts vs lo frequency after 25c calibration for gain tempcomp off worst-case lo leakage over five parts vs lo frequency after 25c calibration for gain tempcomp on temperature sensing diode voltage cumulative distribution worst - case side- band suppression over five parts vs lo frequency after 25c calibration for gain tempcomp on worst-case lo leakage over five parts vs lo frequency after 25c calibration for gain tempcomp off lo leakage vs lo frequency for gain tempcomp on supply current cumulative distribution v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. lo frequency (mhz) 50 lo leakage (dbm) ?40 ?45 ?50 ?55 ?60 ?65 ?70 1050 1250 450 250 850 5599 g64 650 2.7v, 25c 3.3v, 25c 3.6v, 25c 3.3v, 85c 3.3v, 105c 3.3v, ?10c 3.3v, ?40c diode voltage for 100a (v) 0.6 percentage (%) 100 80 60 40 20 0 0.85 0.9 0.7 0.65 0.8 5599 g71 0.75 105c ?40c 25c supply current (ma) 24 percentage (%) 100 80 60 40 20 0 30 32 34 26 5599 g72 28 105c ?40c 25c lo frequency (mhz) 50 lo leakage (dbm) ?40 ?50 ?60 ?70 ?80 1050 1250 450 250 850 5599 g65 650 tempupdt = 1 worst-case: 3.3v, 105c best-case: 3.3v, 25c 3.3v, 25c; 3.3v, 85c; 3.3v, 105c; 3.3v, ?10c; 3.3v, ?40c; 2.7v, 25c and 3.6v, 25c between worst-case and best-case lo frequency (mhz) 50 lo leakage (dbm) ?40 ?50 ?60 ?70 ?80 1050 1250 450 250 850 5599 g66 650 worst-case: 3.3v, 105c best-case: 3.3v, 25c 3.3v, 25c; 3.3v, 85c; 3.3v, 105c; 3.3v, ?10c; 3.3v, ?40c; 2.7v, 25c and 3.6v, 25c between worst-case and best-case lo frequency (mhz) 50 side-band suppression (dbc) ?30 ?40 ?50 ?60 ?70 1050 1250 450 250 850 5599 g67 650 worst-case: 3.3v, 105c best-case: 3.3v, 25c 3.3v, 25c; 3.3v, 85c; 3.3v, 105c; 3.3v, ?10c; 3.3v, ?40c; 2.7v, 25c and 3.6v, 25c between worst-case and best-case tempupdt = 1 lo frequency (mhz) 50 side-band suppression (dbc) ?30 ?40 ?50 ?60 ?70 1050 1250 450 250 850 5599 g68 650 worst-case: 3.3v, 105c best-case: 3.3v, 25c 3.3v, 25c; 3.3v, 85c; 3.3v, 105c; 3.3v, ?10c; 3.3v, ?40c; 2.7v, 25c and 3.6v, 25c between worst-case and best-case rf frequency (mhz) 50 lo leakage (dbm) ?40 ?50 ?60 ?70 ?80 1050 1250 450 250 850 5599 g69 650 dg = 0 dg = ?3 dg = ?4 dg = ?8 dg = ?17 dg = ?19 rf frequency (mhz) 50 side-band suppression (dbc) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 1050 1250 450 250 850 5599 g70 650 dg = 0 dg = ?4 dg = ?19 dg = ?3 dg = ?12 ltc 5599 5599f 14 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics noise floor cumulative distribution gain cumulative distribution for v ctrl = 1.75v gain cumulative distribution for gain tempcomp on lo leakage cumulative distribution for floating baseband pins output ip2 cumulative distribution output ip3 cumulative distribution gain cumulative distribution for v ctrl = 1v gain cumulative distribution for gain tempcomp off sleep current cumulative distribution v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. sleep current (a) 0 percentage (%) 100 80 60 40 20 0 0.6 1 1.2 1.4 1.6 1.8 0.8 2 0.2 0.4 105c ?40c 25c 5599 g73 gain (db) ?8.4 percentage (%) 100 80 60 40 20 0 ?7.2 ?6.8 ?7.6 ?6.4 ?8 130c ?40c tempupdt = 1 25c 5599 g74 gain (db) ?8.4 percentage (%) 100 80 60 40 20 0 ?7.2 ?6.8 ?7.6 ?6.4 ?8 105c ?40c 25c 5599 g75 gain (db) ?18 percentage (%) 100 80 60 40 20 0 ?12 ?14 ?10 ?16 105c ?40c 25c 5599 g76 agctrl = 1 gain (db) ?80 percentage (%) 100 80 60 40 20 0 ?60 ?50 ?70 105c ?40c 25c 5599 g77 agctrl = 1 output ip3 (dbm) 15 percentage (%) 100 80 60 40 20 0 19 21 23 17 105c ?40c 25c 5599 g78 note 11 output ip2 (dbm) 50 percentage (%) 100 80 60 40 20 0 58 62 66 70 74 78 54 ?40c 25c 5599 g79 note 11 105c noise floor (dbm/hz) ?160 percentage (%) 100 80 60 40 20 0 ?156 ?154 ?152 ?158 ?40c 25c 5599 g80 105c lo leakage (dbm) ?60 percentage (%) 100 80 60 40 20 0 ?45 ?40 ?35 ?50 ?55 ?40c 25c 5599 g81 105c ltc 5599 5599f 15 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics side-band suppression cumulative distribution for v ctrl = 1.75v lo return loss side-band suppression cumulative distribution lo leakage cumulative distribution for v ctrl = 1.75v rf return loss lo leakage cumulative distribution v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. lo return loss for 30mhz and 70mhz match, schematic in figure 3 lo leakage (dbm) ?60 percentage (%) 100 80 60 40 20 0 ?45 ?40 ?35 ?50 ?55 ?40c 25c 5599 g82 105c lo leakage (dbm) ?60 percentage (%) 100 80 60 40 20 0 ?45 ?40 ?20 ?35 ?30 ?25 ?50 ?55 ?40c 25c 5599 g83 105c agctrl = 1 side-band suppression (dbc) ?60 percentage (%) 100 80 60 40 20 0 ?50 ?45 ?40 ?35 ?55 ?40c 25c 5599 g84 105c side-band suppression (dbc) ?60 percentage (%) 100 80 60 40 20 0 ?50 ?45 ?40 ?35 ?55 ?40c 25c 5599 g85 105c agctrl = 1 rf frequency (mhz) s 22 (db) 5599 g86 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 10 1000 100 dg = ?18 dg = ?17 dg = ?19 resonance frequency with c4 = 10nf dg = 0 lo frequency (mhz) s 11 (db) 5599 g88 0 ?5 70mhz ?10 ?15 ?20 ?25 ?30 ?35 10 100 register 0x00 set to 0x7f 30mhz lo frequency (mhz) s 11 (db) 5599 g87 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 10 1000 100 register 0x00 set according to lo frequency table 5 ltc 5599 5599f 16 for more information www.linear.com/LTC5599 typical p er f or m ance c harac t eris t ics peak evm vs rf output power with 1ms/s 16-qam signal v cc = 3.3v, en = 3.3v, v ctrl = 3.3v, t c = 25c, p lo = 0dbm, f lo = 500mhz, bbpi, bbmi, bbpq, bbmq common mode dc voltage v cmbb = 1.4v dc , i and q baseband input signal = 2mhz, 2.1mhz, 1v p-p( diff, i or q) , i and q 90 shifted, lower sideband selection, tempupdt = 0, register 0 x 00 value according to table 5, all other registers set to default values, unless otherwise noted. test circuit is shown in figure 13. lo return loss for standard, 900mhz and 1260mhz match rms evm vs rf output power with 1ms/s 16-qam signal lo frequency (mhz) s 11 (db) 5599 g89 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 500 700 900 1100 1300 1500 1700 1900 standard reg 0x00 = 0x0a, l1 = 39nh, c5 = 15pf 900mhz reg 0x00 = 0x12, l1 = 8.2nh, c5 = 3.3pf 1260mhz reg 0x00 = 0x01, l1 = 5.6nh, c5 = 3pf solid: en = high; dashed: en = low standard 900mhz 1260mhz rf power (dbm) evm peak (%) 5599 g91 20 15 10 5 0 ?20 ?16 ?12 ?8 ?4 0 4 dg = ?16 dg = ?12 dg = ?10 dg = ?8 dg = ?6 dg = ?4 dg = ?2 dg = 0 dg = ?19 rf power (dbm) rms evm (%) 5599 g90 10 9 8 7 6 5 4 3 2 1 0 ?20 ?16 ?12 ?8 ?4 0 4 dg = ?16 dg = ?12 dg = ?10 dg = ?8 dg = ?6 dg = ?4 dg = ?2 dg = 0 dg = ?19 ltc 5599 5599f 17 for more information www.linear.com/LTC5599 p in func t ions v ctrl (pin 1): variable gain control input. this analog control pin sets the gain. write a 1 to bit 6 in register 0x 01 (agctrl = 1) to activate this pin, resulting in about 2.58ma current draw from a positive supply. typical v ctrl voltage range is 0.9 v to 3.3 v. gain transfer function is not linear-in-db. tie to v cc when not used. gnd (pins 2, 5, 12, exposed pad 25): ground. all these pins are connected together internally. for best rf perfor - mance all ground pins should be connected to rf ground. lol, loc ( pins 3, 4): lo inputs. this is not a differen- tial input . both pins are 50 inputs. an lc diplexer is recommended to be used at these pins ( see figure 13). ac-coupling capacitors are required at these pins if the applied dc level is higher than 100mv. ttck (pin 6): temperature update. when the ttck tem - perature update mode is selected in register 0x01 (bit 7 = high, tempupdt = 1), the temperature readout and digital gain compensation vs temperature can be updated through a logic low to logic high transition at this pin. do not float. temp (pin 7): temperature sensing diode. this pin is connected to the anode of a diode that may be used to measure the die temperature, by forcing a current and measuring the voltage. this diode is not part of the on- chip thermometer. bbpi, bbmi (pins 8, 9): baseband inputs of the i-channel. the input impedance of each input is about 1 k. it should be externally biased to a 1.4 v common mode level, or ac- coupled. do not apply common mode voltage beyond 2 v dc . bbpq, bbmq ( pins 10, 11): baseband inputs of the q-channel. the input impedance of each input is about 1k. it should be externally biased to a 1.4 v common mode level, or ac-coupled. do not apply common mode voltage beyond 2v dc . float if q-channel is disabled. gndrf (pins 13, 14, 15, 17, 18): rf ground. these pins are connected together internally. for best rf performance all ground pins should be connected to rf ground. rf (pin 16): rf output. the output impedance at rf frequencies is 50. its dc output voltage is about 1.7v if enabled. an ac-coupling capacitor should be used at this pin with a recommended value of 10nf. csb (pin 19): serial port chip select. this cmos input initiates a serial port transaction when driven low, ending the transaction when driven back high. do not float. sclk (pin 20): serial port clock. this cmos input clocks serial port input data on its rising edge. do not float. sdi (pin 21): serial port data input. the serial port uses this cmos input for data. do not float. sdo (pin 22): serial port data output. this nmos output presents data from the serial port during a read transaction. connect this pin to the digital supply voltage through a pull-up resistor of sufficiently large value, to ensure that the current does not exceed 10ma when pulled low. en (pin 23): enable pin. the chip is completely turned on when a logic high voltage is applied to this pin, and completely turned off for a logic low voltage. do not float. v cc (pin 24): power supply. it is recommended to use 1nf and 4.7 f capacitors for decoupling to ground on this pin. ltc 5599 5599f 18 for more information www.linear.com/LTC5599 b lock diagra m 90 0 i-channel q-channel rf en lol loc thermometer 16 3 7 25 gnd 5 2 11 10 9 8 22 sclk 24 bbpi bbmi bbpq bbmq 21 20 19 csb 1 4 5599 bd gndrf 6 15 v cc ttck 18 13 14 17 sdi sdo temp 12 23 spi v ctrl v i v i ltc 5599 5599f 19 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion the LTC5599 consists of i and q input differential voltage- to-current converters, i and q upconverting mixers, an rf output buffer and an lo quadrature phase generator. an spi bus addresses nine control registers, enabling optimization of side-band suppression, lo leakage, and adjustment of the modulator gain. see table 1 for a sum - mary of the writable registers and their default values. a full map of all the registers in the LTC5599 is listed in table 10 and table 11 in the appendix. table 1. spi writable registers and default register values. address default value setting register function 0x00 0x2e 490mhz lo frequency tuning 0x01 0x84 dg = C4 gain 0x02 0x80 0mv offset i-channel 0x03 0x80 0mv offset q-channel 0x04 0x80 0db i/q gain ratio 0x05 0x10 0 i/q phase balance 0x06 0x50 off lo port matching override 0x07 0x06 off temperature correction override 0x08 0x00 normal operating mode without using the spi the registers will use the default values which may not result in the optimum side-band suppression ( sb). for example: for lo frequency from about 400 mhz to about 580 mhz, the sb is about C45dbc; from 380 mhz to 400 mhz and 580 mhz to 630 mhz it falls to about C40 dbc; from 350 mhz to 380 mhz and 630mhz to 690mhz the sb falls to about C35dbc. aside of powering up the LTC5599, the register values can be reset to the default values by setting sreset = 1 (bit 3, register 0 x08). after about 50 ns sreset is automatically set back to 0. external i and q baseband signals are applied to the dif - ferential baseband input pins: bbpi, bbmi and bbpq, bbmq. these voltage signals are converted to currents and translated to rf frequency by means of double-balanced upconverting mixers. the mixer outputs are combined at the inputs of the rf output buffer, which also transforms the output impedance to 50. the center frequency of the resulting rf signal is equal to the lo signal frequency. the lo inputs drive a phase shifter which splits the lo signal into in- phase and quadrature signals which drive the upconverting mixers. in most applications, the lol input is driven by the lo source via a 39 nh inductor, while the loc input is driven by the lo source via a 15 pf capacitor. this inductor and capacitor form a diplexer circuit tuned to 200 mhz. the rf output is single-ended and internally 50 matched across a wide rf frequency range from 0.6mhz to 6 ghz with better than 10 db return loss using c4 = 10nf. see figure 13. baseband interface the baseband inputs ( bbpi, bbmi, bbpq, bbmq) present a differential input impedance of about 1.8 k, as depicted in figure 1. the baseband bandwidth depends on the source impedance and the frequency setting (register 0x00). it is recommended to compensate the baseband input impedance in the baseband lowpass filter design in order to achieve best gain flatness vs baseband frequency. the s-parameters for ( each of) the baseband inputs are given in table 2 for various lo frequency and gain settings. figure 1. simplified circuit schematic of the base band input interface (only one channel is shown). bbpi bbmi 5599 f01 40 1k 3pf v cm = 1.4v v cc = 3.3v 1k 40 3pf v ctrl 35 10pf 1 8 9 2.5ma 1.4v en + ltc 5599 5599f 20 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion t able 2. differential baseband (bb) input impedance vs frequency for en = high and v cmbb = 1.4v bb frequency (mhz) input impedance (w ) refl coefficient real* imag* (cap) mag angle lo frequency = 92mhz ( register 0 x 00 = 0x 79), digital gain = C4db 1 1.90k C7.17k (22.2pf) 0.900 C1.6 4 1.76k C1.82k (21.9pf) 0.893 C6.3 10 1.25k C751 (21.2pf) 0.854 C15 20 678 C429 (18.6pf) 0.755 C27 40 342 C308 (12.9pf) 0.585 C39 lo frequency = 150mhz ( register 0 x 00 = 0x 62), digital gain = C4db 1 1.90k C9.11k (17.5pf) 0.900 C1.3 4 1.82k C2.30k (17.3pf) 0.896 C5.0 10 1.45k C935 (17.0pf) 0.872 C12 20 887 C507 (15.7pf) 0.804 C23 40 441 C325 (12.2pf) 0.658 C36 100 226 C252 (6.3pf) 0.457 C51 lo frequency = 500mhz ( register 0 x 00 = 0 x2d ), digital gain = C4db 1 1.91k C14.7k (10.6pf) 0.900 C0.8 4 1.89k C3.74k (10.7pf) 0.899 C3.0 10 1.72k C1.50k (10.7pf) 0.891 C7.7 20 1.35k C769 (10.4pf) 0.864 C15 40 786 C426 (9.4pf) 0.785 C27 100 323 C251 (6.4pf) 0.583 C47 200 212 C190 (4.2pf) 0.478 C65 lo frequency = 500mhz ( register 0 x 00 = 0 x2d ), digital gain = 0db 1 1.56k C15.0k (10.6pf) 0.879 C0.8 4 1.56k C3.84k (10.4pf) 0.880 C3.0 10 1.48k C1.52k (10.4pf) 0.874 C7.5 20 1.21k C784 (10.2pf) 0.849 C15 40 753 C432 (9.2pf) 0.776 C27 100 323 C251 (6.3pf) 0.582 C47 200 213 C190 (4.2pf) 0.478 C65 lo frequency = 900mhz ( register 0 x 00 = 0x 12), digital gain = C4db 1 1.91k C17.0k (9.4pf) 0.901 C0.7 2 1.90k C4.3k (9.3pf) 0.900 C2.7 10 1.77k C1.72k (9.3pf) 0.893 C6.7 20 1.46k C878 (9.1pf) 0.873 C13 40 915 C475 (8.4pf) 0.811 C24 100 371 C261 (6.1 pf) 0.622 C45 200 233 C193 (4.1pf) 0.506 C62 t able 2. differential baseband (bb) input impedance vs frequency for en = high and v cmbb = 1.4v bb frequency (mhz) input impedance (w ) refl coefficient real* imag* (cap) mag angle en = low (chip disabled, register 0x00 = 0x2e) 1 2.04k C18.2k (8.8pf) 0.906 C0.6 2 2.02k C4.59k (8.7pf) 0.906 C2.5 10 1.91k C1.84k (8.7pf) 0.901 C6.3 20 1.59k C935 (8.5pf) 0.893 C12 40 1.01k C502 (7.9pf) 0.826 C23 100 402 C269 (5.9pf) 0.644 C43 200 246 C197 (4.0pf) 0.522 C60 *parallel equivalent the circuit is optimized for a common mode voltage of 1.4v which can be internally or externally applied. in case of ac- coupling to the baseband pins (1.4 v internally generated bias) make sure that the high pass filter corner is not affecting the low frequency components of the baseband signal. even a small error for low baseband frequencies can result in degraded evm. the baseband input offset voltage depends on the source resistance. in case of ac-coupling the 1 sigma offset is about 1.1 mv, resulting in about C46.6 dbm lo leakage. for shorted baseband pins (0 source resistance), the lo leakage improves to about C50.1 dbm. in case of ac- coupling the lo leakage can be reduced by connecting a resistor in parallel with the baseband inputs, thus lower - ing baseband input impedance and offset. further, the low combined baseband input leakage current of 1.3 na in shutdown mode retains the voltage over the coupling capacitors, which helps to settle faster when the part is enabled again. it is recommended to drive the baseband inputs differentially to improve the linearity. when a dac is used as the signal source, a reconstruction filter should be placed between the dac output and the LTC5599 baseband inputs to avoid aliasing. internal gain trim dacs four internal gain trim dacs ( one for each baseband pin) are configured as 11- bit each. the usable dac input value range is integer continuous from 64 to 2047 and 0 for shutdown. the dacs are not intended for baseband signal (continued) ltc 5599 5599f 21 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion generation but for gain and offset setting only, because there are no reconstruction filters between the dacs and the mixer core, and there is only indirect access between the dac values and the register settings. the following functions are implemented in this way: ? coarse digital gain control with 1db steps ? fine digital gain control with 0.1db steps ? gain-temperature correction ? dc offset adjustment in the i-channel ? dc offset adjustment in the q-channel ? i/q gain balance control ? disable q-channel ? continuous variable gain control coarse digital gain control ( dg) with 1 db steps ( register 0 x 01) twenty digital gain positions 1 db apart are implemented by hardwiring a corresponding dac code for all four dacs. the coarse digital gain is set by writing to the five least-significant bits in register 0 x01, see table 10 and 11. the gain is the highest for code 00000 (code 0 = 0 db, dg = 0) and the lowest for code 10011 ( code 19 = C19db, dg = C19). note that the gain 0 db set by the digital gain control is not the same as the voltage gain of the part. the remaining 12 codes (decimal 20 to 31) are reserved. the digital gain in db equals minus the decimal value writ - ten into the 5 least-significant bits of the gain register. the formula relating the modulator gain g(in v/v) relative to the maximum conversion gain therefore equals: g(v/v) = 10 (dg/20) fine digital gain control(fdg) with 0.1db steps and gain-temperature correction (register 0x07) sixteen digital gain positions about 0.1 db apart can be set directly using the four least-significant bits in register 0 x 07 combined with bit 2 = 1 in register 0x08 (tempcorr = 1). for coarse digital gain settings code 9 and higher some or more subsequent codes of the fine digital gain positions may be the same due to the limited resolution of the 11- bit dacs. the main purpose of these 0.1 db gain steps is to implement an automatic gain/temperature correction which can be activated by setting tempcorr = 1. in that case, the input of the fine digital gain control will be the on- chip thermometer. the on- chip thermometer generates a 4- bit digital code with code 0 corresponding to C30c and code 15 corresponding to 120 c and 10 c spacing between the codes. the on-chip thermometer output code can be updated continuous ( by clearing tempupdt, bit 7 in register 0 x01, see table 10) or can be updated by bring - ing the external pin ttck from low to high (and setting tempup td = 1). in case of continuous update the code will be an asynchronous update whenever the temperature crosses a certain threshold. in some cases it is desired to prevent a gain update to happen in the middle of a data frame. in that case, the gain/temperature update can be synchronized using the ttck pin for example at the begin - ning or end of a data frame. the on-chip temperature can be read back by reading register 0x1f (temp[3:0]).the decimal value of temp[3:0] is given by: temp[3:0] = round(t/10) + 3 with t the actual on-chip temperature in c. its accuracy is about 10 c. temp[3:0] defaults to 7 after an en low to high transition with tempupdt = 1. switching from tempupdt = 0 to temptupdt = 1, temp[3:0] indicates the temperature during the last time ttck went from low to high. note that the actual on-chip temperature cannot be read if tempcorr = 1 or when tempupdt = 1 without toggling ttck. analog gain control the LTC5599 supports analog control of the conversion gain through a voltage applied to v ctrl ( pin 1). the gain can be controlled downward from the digital gain setting (dg) programmed in register 0 x01. in order to minimize distortion in the rf output signal the agctrl bit (bit 6 in register 0x01) should be set to 1. if analog gain control is not used, v ctrl should be connected to v cc and agctrl set to 0; this saves about 2.58 ma of supply current. the typical usable gain control range is from 0.9 v to 3.3v. setting v ctrl to a voltage lower than v cc with agctrl = 0 significantly impairs the linearity of the rf output signal and lowers the v ctrl response time. a simplified schematic is shown in figure 1. ltc 5599 5599f 22 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion i/q dc offset adjustment ( registers 0 x 02 and 0 x 03) and lo leakage offsets in the i- and q-channel translates into lo leakage at the rf port. this offset can either be caused by the i/q modulator or, in case the baseband connections are dc-coupled, applied externally. registers 0 x02 and 0x03 (i-offset and q-offset) can be set to cancel this offset and hence lower the lo leakage. to adjust the offset in the i-channel, the bbpi dac is set to a ( slightly) different value than the bbmi dac, introducing an offset. these 8-bit registers defaults are 128 and represents 0 offset. the register value can be set from 1 to 255. the value 0 represents an unsupported code and should not be used. since the input referred offset depends on the gain the input offset value (v os ) can be calculated as: v os = 1260/((3632 ? g)/(n os C 128) C (n os C 128) /(3632 ? g)) and v os = 0 for n os =128. g represents the gain from table 3. table 3. coarse digital gain (dg) register settings. dg (db) g(v/v) dec binary hex 0 1.000 0 00000 0x00 C1 0.891 1 00001 0x01 C2 0.794 2 00010 0x02 C3 0.708 3 00011 0x03 C4 0.631 4 00100 0x04 C5 0.562 5 00101 0x05 C6 0.501 6 00110 0x06 C7 0.447 7 00111 0x07 C8 0.398 8 01000 0x08 C9 0.355 9 01001 0x09 C10 0.316 10 01010 0x0a C11 0.282 11 01011 0x0b C12 0.251 12 01100 0x0c C13 0.224 13 01101 0x0d C14 0.200 14 01110 0x0e C15 0.178 15 01111 0x0f C16 0.158 16 10000 0x10 C17 0.141 17 10001 0x11 C18 0.126 18 10010 0x12 C19 0.112 19 10011 0x13 a positive offset means that the voltage of the positive input terminal ( bbpi or bbpq) is increased relative to the negative input terminal (bbmi or bbmq). i/q gain ratio (register 0x04) and side-band suppression the 8- bit i/q gain ratio register 0 x04 controls the ratio of the i-channel mixer conversion gain g i and the q-channel mixer conversion gain g q . together with the quadrature phase imbalance register 0 x 05, register 0 x 04 allows further optimization of the modulator side-band suppression. the expression relating the gain ratio g i /g q to the contents of the 8- bit register 0 x04, represented by decimal n iq and the nominal conversion gain g equals: 20 log (g i /g q ) = 20 log ((3632 ? g C (n iq C 128))/ (3632 ? g +(n iq C128))) (db) the step size of the gain ratio trim in db vs n iq is ap- proximately constant for the same digital gain setting. for digital gain setting = C4, for example, the step size is about 7.6 mdb. table 4 lists the gain step size for each digital gain setting that follows from the formula above. table 4. i/q gain ratio step size vs digital gain setting dg (db) g (v/v) ?g i /g q (mdb) 0 1.000 4.8 C1 0.891 5.4 C2 0.794 6.0 C3 0.708 6.8 C4 0.631 7.6 C5 0.562 8.5 C6 0.501 9.6 C7 0.447 10.7 C8 0.398 12.0 C9 0.355 13.5 C10 0.316 15.1 C11 0.282 17.1 C12 0.251 19.2 C13 0.224 21.5 C14 0.200 24.2 C15 0.178 27.3 ltc 5599 5599f 23 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion table 4. i/q gain ratio step size vs digital gain setting dg (db) g (v/v) ?g i /g q (mdb) C16 0.158 30.7 C17 0.141 34.6 C18 0.126 39.0 C19 0.112 44.1 the conversion gain of the i-channel and q-channel are equal for n iq = 128. the i-channel gain is larger than the q-channel gain for n iq > 128. disable q-channel if bit 5 in register 0x01 ( qdisable) is set, the q-channel is switched off, turning the i/q modulator into an upcon - version mixer. it is recommended to float the bbpq and bbmq pins in this mode. the default mode is q-channel is on (qdisable = 0). lo section (register 0x00) the internal lo chain consists of a poly-phase filter which generates the i and q signals for the image-reject double- balanced mixer. the center frequency of the poly-phase filter is set by the lower seven bits of register 0 x00. the recommended settings vs lo frequency are given in table 5 (see the quikeval? gui). table 5. register 0x00 setting vs lo frequency register value lo frequency range (mhz) decimal binary hex lower bound upper bound 0 0000000 00 n/a n/a 1 0000001 01 1249.1 1300.0 2 0000010 02 1248.6 1249.0 3 0000011 03 1238.1 1248.5 4 0000100 04 1214.1 1238.0 5 0000101 05 1191.2 1214.0 6 0000110 06 1165.6 1191.1 7 0000111 07 1141.0 1165.5 8 0001000 08 1120.6 1140.9 9 0001001 09 1100.5 1120.5 10 0001010 0a 1069.5 1100.4 11 0001011 0b 1039.6 1069.4 12 0001100 0c 1023.1 1039.5 13 0001101 0d 1007.1 1023.0 14 0001110 0e 988.3 1007.0 (continued) table 5. register 0x00 setting vs lo frequency register value lo frequency range (mhz) decimal binary hex lower bound upper bound 15 0001111 0f 961.8 988.2 16 0010000 10 941.3 961.7 17 0010001 11 921.5 941.2 18 0010010 12 895.2 921.4 19 0010011 13 877.6 895.1 20 0010100 14 863.6 877.5 21 0010101 15 843.2 863.5 22 0010110 16 826.9 843.1 23 0010111 17 807.0 826.8 24 0011000 18 792.3 806.9 25 0011001 19 772.2 792.2 26 0011010 1a 752.7 772.1 27 0011011 1b 734.0 752.6 28 0011100 1c 724.2 739.9 29 0011101 1d 704.6 724.1 30 0011110 1e 688.7 704.5 31 0011111 1f 673.2 688.6 32 0100000 20 655.2 673.1 33 0100001 21 638.1 655.1 34 0100010 22 624.6 638.0 35 0100011 23 611.9 624.5 36 0100100 24 598.4 611.8 37 0100101 25 585.1 598.3 38 0100110 26 573.9 585.0 39 0100111 27 563.1 573.8 40 0101000 28 548.1 563.0 41 0101001 29 538.1 548.0 42 0101010 2a 529.1 538.0 43 0101011 2b 518.5 529.0 44 0101100 2c 507.0 518.4 45 0101101 2d 497.7 506.9 46 0101110 2e 488.0 497.6 47 0101111 2f 471.5 487.9 48 0110000 30 457.7 471.4 49 0110001 31 448.7 457.6 50 0110010 32 437.4 448.6 51 0110011 33 426.6 437.3 52 0110100 34 417.5 426.5 53 0110101 35 407.5 417.4 54 0110110 36 398.0 407.4 (continued) ltc 5599 5599f 24 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion table 5. register 0x00 setting vs lo frequency register value lo frequency range (mhz) decimal binary hex lower bound upper bound 96 1100000 60 153.6 156.6 97 1100001 61 151.1 153.5 98 1100010 62 148.6 151.0 99 1100011 63 142.5 148.5 100 1100100 64 139.6 142.4 101 1100101 65 136.5 139.5 102 1100110 66 134.3 136.4 103 1100111 67 131.2 134.2 104 1101000 68 128.1 131.1 105 1101001 69 126.0 128.0 106 1101010 6a 123.8 125.9 107 1101011 6b 121.3 123.7 108 1101100 6c 118.3 121.2 109 1101101 6d 115.7 118.2 110 1101110 6e 113.5 115.6 111 1101111 6f 111.3 113.4 112 1110000 70 109.5 111.2 113 1110001 71 107.6 109.4 114 1110010 72 105.6 107.5 115 1110011 73 103.0 105.5 116 1110100 74 100.3 102.9 117 1110101 75 98.5 100.2 118 1110110 76 96.6 98.4 119 1110111 77 94.7 96.5 120 1111000 78 93.0 94.6 121 1111001 79 30.0 92.9 122 1111010 7a n/a n/a 123 1111011 7b n/a n/a 124 1111100 7c n/a n/a 125 1111101 7d n/a n/a 126 1111110 7e n/a n/a 127 1111111 7f n/a n/a a simplified circuit schematic of the lol and loc inter- faces is depicted in figure 2. the lol and loc inputs are not differential lo inputs. they are 50 inputs and are intended to be driven with an inductor going to the lol input and a capacitor to the loc input. do not switch the capacitor and inductor, as this will result in very poor performance. for a wideband lo range an inductor value of 39 nh and a capacitor value of 15pf ( standard lo match) table 5. register 0x00 setting vs lo frequency register value lo frequency range (mhz) decimal binary hex lower bound upper bound 55 0110111 37 390.1 397.9 56 0111000 38 382.8 390.0 57 0111001 39 376.6 382.7 58 0111010 3a 369.8 376.5 59 0111011 3b 353.1 369.7 60 0111100 3c 339.0 353.0 61 0111101 3d 332.6 338.9 62 0111110 3e 327.2 332.5 63 0111111 3f 320.6 327.1 64 1000000 40 313.7 320.5 65 1000001 41 309.1 313.6 66 1000010 42 304.5 309.0 67 1000011 43 288.1 304.4 68 1000100 44 278.3 288.0 69 1000101 45 274.2 278.2 70 1000110 46 270.3 274.1 71 1000111 47 266.0 270.2 72 1001000 48 261.9 265.9 73 1001001 49 258.2 261.8 74 1001010 4a 254.1 258.1 75 1001011 4b 243.6 254.0 76 1001100 4c 233.8 243.5 77 1001101 4d 230.8 233.7 78 1001110 4e 228.0 230.7 79 1001111 4f 220.2 227.9 80 1010000 50 212.6 220.1 81 1010001 51 210.0 212.5 82 1010010 52 207.6 209.9 83 1010011 53 202.1 207.5 84 1010100 54 196.2 202.0 85 1010101 55 193.7 196.1 86 1010110 56 191.2 193.6 87 1010111 57 186.6 191.1 88 1011000 58 182.0 186.5 89 1011001 59 179.4 181.9 90 1011010 5a 176.0 179.3 91 1011011 5b 170.1 175.9 92 1011100 5c 165.0 170.0 93 1011101 5d 162.5 164.9 94 1011110 5e 160.0 162.4 95 1011111 5f 156.7 159.9 (continued) (continued) ltc 5599 5599f 25 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion figure 2. simplified circuit schematic for the lol and loc inputs is recommended at these pins, forming a diplexer circuit with center frequency of 200 mhz. this diplexer helps to improve the uncalibrated side-band suppression signifi - cantly around 200 mhz. even for lo frequencies far from 200mhz the diplexer performs better than a single-ended lo drive or a differential drive. due to factory calibration of the poly-phase filter the typical side-band suppression is about 50 dbc for frequencies from 100 mhz to 700mhz and 45 dbc from 700 mhz to 1300 mhz. for narrow-band applications far from 200 mhz it may help to tune the diplexer to a different frequency which can improve the uncalibrated side-band suppression and the gain vs lo drive level. the typical performance characteristics section shows the return loss for a 900 mhz match (l1 = 8.2nh, c5 = 3.3 pf) and a 1260 mhz match (l1 = 5.6 nh, c5 = 3pf). to get a performance with the standard 200 mhz match equivalent to the 900 mhz and 1260 mhz match, the lo power should be increased by 1.5 db and 2 db respectively. register 0 x00 values of table 5 may have to be adjusted as well, in case the standard match is not used. loc lol 5599 f02 3 4 5599 f03 3 4 30mhz/70mhz figure 3. impedance matching network for lol and loc interfaces matched at 30mhz/70mhz table 6 lists lol and loc port input impedance vs frequency at en = high and p lo = 0 dbm. the other lo port ( loc or lol) is terminated in a 50. table 6. lol, loc port input impedance vs frequency for en = high and p lo = 0dbm (other lo port terminated with 50 to ground) freq (mhz) reg 0x00 lol/loc port impedance ( w ) refl coefficient real* imag* (ind) mag angle 20 79 7.9 24.3 (194nh) 0.750 175 30 79 9.1 19.0 (101nh) 0.743 172 40 79 10.8 17.4 (69nh) 0.732 169 50 79 13.0 17.6 (56nh) 0.716 165 60 79 15.7 18.9 (50nh) 0.693 162 70 79 18.6 21.4 (49nh)) 0.661 158 80 79 21.6 25.0 (50nh) 0.618 154 90 79 24.4 30.3 (54nh) 0.564 151 100 75 27.0 38.3 (61nh)) 0.497 148 110 70 29.0 51.4 (74nh) 0.419 146 120 6c 30.3 76.1 (101nh) 0.338 149 130 68 32.3 109.3 (134nh) 0.276 150 140 64 34.3 121.6 (138nh) 0.247 148 150 62 36.2 119.4 (127nh) 0.234 142 160 5e 37.4 149.1 (148nh)) 0.201 143 170 5c 37.1 357.5 (335nh) 0.160 162 180 59 39.6 188.6 (167nh) 0.164 141 190 57 41.4 192.0 (161nh)) 0.150 135 200 54 40.7 418.6 (333nh) 0.116 156 *parallel equivalent the circuit schematic of the demo board is shown in figure 13. i/q phase balance adjustment register 0x05 and side-band suppression ideally the i-channel lo phase is exactly 90 ahead of the q- channel lo phase, so called quadrature. in practice how - ever, the i/q phase difference differs from exact quadrature by a small error due to component parameter variations and harmonic content in the lo signal (see below). the i/q phase imbalance register (0 x05) allows adjust - ment of the i/q phase shift to compensate for such errors. together with gain ratio register 0 x04, it can thus be used to optimize the side-band suppression of the modulator. below 100 mhz the matching network of figure 3 can be used.the side-band suppression in that case is largely defined by the diplexer l1, c5 and the ( temperature de - pendent) lol and loc input impedance. see measured performance in the typical performance characteristics section. l2 120nh/51nh ltc 5599 5599f c19 180pf/47pf l1 47nh/43nh c5 560pf/120pf c20 270pf/100pf lol lo loc c21 270pf/100pf 26 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion register 0 x05 contains two parts ( see table 11); the five least significant bits iqphf realize a fine phase adjustment, while the three most significant bits iqphe are used for coarse adjustments. the fine phase adjustment realized by iqphf can be approximated as: j iq = C ((n ph C16)/15) ? ln(f lo /50) (degrees) for 30mhz < f lo < 1300mhz where n ph is the decimal value of iqphf and f lo is the frequency of the lo signal in mhz. a positive value for j iq means that the i-channel lo phase is more than 90 ahead of the q-channel lo phase. notice from the expres- sion that the phase adjustment range and resolution are coupled, and dependent on the lo frequency. at low lo frequencies the the smallest adjustment range and highest resolution is achieved, while high lo frequencies exhibit the largest range and lowest resolution. the extension bits iqphe provide a larger phase adjust - ment range, particularly useful at lower lo frequencies, and overcome another trade- off; between phase adjustment range and the maximum center frequency of the poly- phase filter. the latter trade-off is due to the fact that the capacitances in the i- channel, c ppi , and q- channel, c ppq , of the poly-phase filter control both these parameters. their difference sets the phase shift, while their sum determines the center frequency of the filter. the extension bits iqphe introduce a large phase offset in addition to the fine adjustment realized by the iqphf bits. the sign of this large offset can be positive or negative, controlled by iqphsign (bit 7 in register 0 x00). including these bits, the total phase shift from quadrature can be expressed as: j iq = C (m ph /15) ? ln(f lo /50) (degrees) with m ph = n coarse + n ph C16 and n coarse = 32 ? (C1) iqphsign + 1 ? n ext where n ext equals the decimal value of the iqphe bits. the valid range of values for (n ph C16) is thus expanded from {C16, C15, ... , +15} to {C240, C239, ... , +239}. table 9 in the appendix lists all the possible combinations. the cod - ing ranges for iqphsign = 0 and iqphsign = 1 overlap between m ph = C16 and m ph = +15, such that iqphsign only needs to be changed for larger phase shifts. as a side effect, the extension bits slightly detune the center frequency of the poly-phase filter, after crossing the boundary to a new n coarse value. this can be observed as a large step in the actual phase shift. a solution for this is to decrease the value in the frequency register 0x00 (increase the poly-phase filter center frequency) at the n coarse value boundaries. the result is a smooth phase adjustment. in the demo board quikeval gui, this lo fre- quency register adjustment is automatically taken care of. whenever the poly- phase filter center frequency is adjusted to improve the smoothness of the phase adjustment, it is recommended to manually program the lo port impedance match using the cloo bits in register 0 x06. by default, changing the filter center frequency also automatically adjusts the matching of the lo port ( when cloen, bit 4 in register 0x06 is set). however, since the lo carrier frequency does not change, automatic adjustment of the lo match is undesirable in this case; it may add another large step to the phase adjustment. instead, the lo match should remain unchanged while the filter center frequency is adjusted. this can be achieved as follows. first, the current lo matching configuration is read from the clo bits in register 0 x1d, and written to the cloo override bits in register 0 x06. subsequently, the cloen bit (bit 4, register 0 x06) is cleared to disable automatic lo match adjustment. as a result the center frequency can be ad- justed in register 0x00 without changing the lo match. at 100 mhz the maximum phase shift is about 9.8, while at 1 ghz it is about 3. the extension bits are not useful above 988.2 mhz since the poly-phase center frequency register 0 x00 value cannot be adjusted low enough to ensure a smooth transition to a new n coarse value. square wave lo drive harmonic content of the lo signal adversely affects quadrature phase error and gain accuracy, whenever a poly-phase filter is used for quadrature generation. the LTC5599 can correct for phase and gain errors due to har - monics in the lo carrier ( e.g. in a square wave) by setting appropriate values in the i/q gain and i/q phase registers. such adjustments are typically needed when the 3rd-order harmonic of the lo signal exceeds the desirable side-band suppression minus 13 db. although the poly-phase filter is less sensitive to the second harmonic content of the lo ltc 5599 5599f 27 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion figure 4. simplified circuit schematic for the rf output port carrier, its influence can still be significant. for C15dbc second harmonic content, the side-band suppression can degrade to C45 dbc; for C20 dbc it is C54 dbc, assuming no i/q gain and phase adjustments are made. rf output after upconversion, the rf outputs of the i and q mixers are combined. an on-chip buffer performs internal dif - ferential to single-ended conversion, while transforming the output signal to 50 as shown in figure 4. v cc 5599 f04 16 table 7 shows the rf port output impedance vs frequency and digital gain setting for en = high. table 7. rf output impedance vs frequency and digital gain setting (dg) for en = high frequency (mhz) dg (db) output impedance (w) refl coefficient real* imag* (cap) mag angle 30 0 59 C413 (12.8pf) 0.104 C43 30 C12 61 C465 (11.4pf) 0.114 C35 30 C16 64 C529 (10.0pf) 0.133 C27 30 C18 69 C623 (8.5pf) 0.166 C19 30 C19 83 C902 (5.9pf) 0.249 C10 50 0 56 C671 (4.7pf) 0.068 C38 50 C12 58 C762 (4.2pf) 0.082 C27 50 C16 61 C859 (3.7pf) 0.107 C19 50 C18 67 C972 (3.3pf) 0.146 C13 50 C19 81 C1.21k (2.6pf) 0.239 C8 100 0 55 C1.08k (1.5pf) 0.050 C30 100 C12 57 C1.32k (1.2pf) 0.066 C19 100 C16 60 C1.55k (1.0pf) 0.096 C12 100 C18 66 C1.75k (0.91pf) 0.142 C8 100 C19 82 C1.98k (0.80pf) 0.246 C5 600 0 54 C1.35k (0.20pf) 0.040 C30 600 C12 56 C1.75k (0.15pf) 0.057 C16 table 7. rf output impedance vs frequency and digital gain setting (dg) for en = high frequency (mhz) dg (db) output impedance (w) refl coefficient real* imag* (cap) mag angle 600 C16 58 C1.77k (0.15pf) 0.078 C12 600 C18 62 C1.44k (0.18pf) 0.109 C11 600 C19 77 C680 (0.39pf) 0.217 C14 1300 0 48 C802 (0.15pf) 0.035 C119 1300 C12 51 C807 (0.15pf) 0.034 C68 1300 C16 55 C709 (0.17pf) 0.059 C41 1300 C18 59 C526 (0.23pf) 0.098 C35 1300 C19 73 C280 (0.44pf) 0.215 C36 *parallel equivalent the rf port output impedance for en = low is given in table 8. table 8. rf output impedance vs frequency for en = low frequency (mhz) output impedance (w) refl coefficient real* imag* (cap) mag angle 30 16.1k C7.76k (0.68pf) 0.994 C0.7 40 16.2k C5.24k (0.76pf) 0.994 C1.1 50 15.7k C3.96k (0.80pf) 0.994 C1.4 60 16.5k C3.18k (0.83pf) 0.994 C1.8 70 16.8k C2.66k (0.86pf) 0.994 C2.2 80 16.4k C2.29k (0.87pf) 0.994 C2.5 90 17.1k C2.01k (0.88pf) 0.994 C2.9 100 17.9k C1.79k (0.89pf) 0.994 C3.2 200 14.7k C856 (0.93pf) 0.993 C6.7 250 11.1k C679 (0.94pf) 0.991 C8.4 300 8.55k C563 (0.94pf) 0.988 C10 350 7.97k C481 (0.94pf) 0.988 C12 400 6.42k C420 (0.95pf) 0.985 C14 450 5.27k C373 (0.95pf) 0.982 C15 500 4.26k C336 (0.95pf) 0.977 C17 600 3.05k C281 (0.94pf) 0.969 C20 700 2.32k C241 (0.94pf) 0.959 C23 800 1.85k C211 (0.94pf) 0.950 C27 900 1.54k C188 (0.94pf) 0.941 C30 1000 1.30k C169 (0.94pf) 0.932 C33 1100 1.12k C154 (0.94pf) 0.923 C36 1200 991 C141 (0.94pf) 0.914 C39 1300 881 C129 (0.95pf) 0.906 C42 *parallel equivalent (continued) ltc 5599 5599f rf 50 28 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion master?csb master?sclk t css t cs t ch data data 5599 f06 t ckl t ckh t css t csh master?sdi master?csb master?sclk LTC5599?sdo 5599 f07 8th clock data data t do t do t do t do figure 6. serial port write timing diagram figure 7. serial port read timing diagram 5599 f05 v cc en internal enable circuit 23 serial port the spi - compatible serial port provides control and monitoring functionality. communication sequence the serial bus is comprised of csb, sclk, sdi and sdo. data transfers to the part are accomplished by the for v cc = 3.3 v and en = high the rf pin voltage is about 1.68v. for v cc = 3.3 v and en = low the rf pin voltage is about 3.1v. enable interface figure 5 shows a simplified schematic of the en pin interface. the voltage necessar y to turn on the LTC5599 is 1.1v. to disable ( shut down) the chip, the enable voltage must be below 0.2v. figure 5. simplified circuit schematic of the en interface serial bus master device first taking csb low to enable the LTC5599s port. input data applied on sdi is clocked on the rising edge of sclk, with all transfers msb first. the communication burst is terminated by the serial bus master returning csb high. see figure 6 for details. data is read from the part during a communication burst using sdo. readback may be multidrop ( more than one LTC5599 connected in parallel on the serial bus), as sdo is high impedance ( hi-z) when csb = 1, or when data is not being read from the part . if the ltc 5599 is not used in a multidrop configuration, or if the serial port master is not capable of setting the sdo line level between read sequences, it is recommended to attach a resistor between sdo and v cc_l to ensure the line returns to v cc_l during hi-z states. the resistor value should be large enough to ensure that the sdo output current does not exceed 10ma. see figure 7 for details. single byte transfers the serial port is arranged as a simple memory map, with status and control available in 9 read/write and 23 read- only byte-wide registers. all data bursts are comprised of at least two bytes. the 7 most significant bits of the first byte are the register address, with an lsb of 1 indicating a read from the part, and lsb of 0 indicating a write to the part. the subsequent byte, or bytes, is data from/to the ltc 5599 5599f 29 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion a6 a5 a4 a3 a2 7-bit register address master?csb master?sclk master?sdi LTC5599?sd0 a1 a0 0 d7 d6 d5 d4 d3 d2 d1 d0 8 bits of data 0 = write 5599 f08 16 clocks parallel load addr0 + wr master?csb master?sdi LTC5599?sdo byte 0 addr1 + wr byte 1 5599 f10 figure 8. serial port write sequence figure 9. serial port read sequence figure 10. serial port single byte writes a6 a5 a4 a3 a2 7-bit register address a1 a0 1 d7x d6 d5 d4 d3 d2 d1 d0 dx 8 bits of data 1 = read 5599 f09 master?csb master?sclk master?sdi LTC5599?sdo 16 clocks specified register address. see figure 8 for an example of a detailed write sequence, and figure 9 for a read sequence. figure 10 shows an example of two write communication bursts. the first byte of the first burst sent from the serial bus master on sdi contains the destination register ad - dress ( addr0) and an lsb of 0 indicating a write. the next byte is the data intended for the register at address addr0. csb is then taken high to terminate the transfer. the first byte of the second burst contains the destination register address ( addr1) and an lsb indicating a write. the next byte on sdi is the data intended for the register at address addr1. csb is then taken high to terminate the transfer. note that the written data is transferred to the internal register at the falling edge of the 16 th clock cycle ( paral- lel load). ltc 5599 5599f 30 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion multiple byte transfers more efficient data transfer of multiple bytes is accom- plished by using the LTC5599s register address auto- increment feature as shown in figure 11. the serial port master sends the destination register address in the first byte and its data in the second byte as before, but continues sending bytes destined for subsequent registers. byte 1s address is addr0+1, byte 2 s address is addr0+2, and so on. if the resister address pointer attempts to increment past 31 (0x1f), it is automatically reset to 0. an example of an auto-increment read from the part is shown in figure 12. the first byte of the burst sent from the serial bus master on sdi contains the destination reg - ister address (addr0) and an lsb of 1 indicating a read. once the LTC5599 detects a read burst, it takes sdo out of the hi-z condition and sends data bytes sequentially, beginning with data from register addr0. the part ignores all other data on sdi until the end of the burst. addr0 + rd don?t care master?csb master?sdi LTC5599?sdo 5599 f12 byte 0 byte 1 byte 2 figure 12. serial port auto-increment read multidrop configuration several LTC5599 s may share the serial bus. in this multidrop configuration, sclk, sdi, and sdo are common between all parts. the serial bus master must use a separate csb for each LTC5599 and ensure that only one device has csb asserted at any time. it is recommended to attach a high value resistor to sdo to ensure the line returns to a known level (v cc_l ) during hi-z states. serial port registers the memory map of the LTC5599 may be found in the appendix in table 10, with detailed bit descriptions found in table 11. the register address shown in hexadecimal format under the addr column is used to specify each register. each register is denoted as either read-only (r) or read-write ( r/w). the registers default value on device power-up or after a reset (bit 3, register 0 x08, sreset) is shown at the right. addr0 + wr master?csb master?sdi LTC5599?sdo byte 0 byte 1 byte 2 5599 f11 figure 11. serial port auto-increment write ltc 5599 5599f 31 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion spi signal levels the spi bus supports signal levels from a digital v cc_l from 1.2 v to 3.6 v. the csb = 1.2 v condition creates an additional static input sleep current of 0.2 a. for csb = 1.8v the extra sleep current can be neglected. evaluation board figure 13 shows the evaluation board schematic. a good ground connection is required for the exposed pad. if this is not done properly, the rf performance will degrade . figures 14 and 15 show the component side and bottom side of the evaluation board. ferrite bead fb1 limits the supply voltage ramping speed in case v cc is abruptly connected to a voltage source. in the application, limit the v cc ramp speed to a maximum of 1v/s. figure 13. evaluation circuit schematic 3 2 1 c4 10nf l1, 39nh c5, 15pf c3 100nf r1, 1 r9 49.9 r8 49.9 c6 100nf c7 100nf r19, 1k r23, 1k r25, 1k r26, 1k lo v ctrl ttck temp bbpi en bbpq sdo en sdi sdo sclk sdi csb sclk gndrf csb gndrf rf rf v cc 2.7v to 3.6v gndrf vcc_l 1.2v to 3.6v gndrf fb1 ferrite bead tdk, mpz1608s331at gndrf board number: dc2091a gnd 5599 f13 bbmq bbmq bbpq bbpq bbmi r10 49.9 bbpi c8 100nf temp r11 49.9 LTC5599iuf c9 100nf 25 c2 1nf 24 c18 2.2pf 23 c13 2.2pf 22 c12 2.2pf 21 c10 2.2pf 20 c1 4.7f 19 c17 100nf 18 r18 1k 17 (r pull-up ) 16 15 14 13 12 11 ltc 5599 10 5599f 9 v ctrl 8 gnd 7 lol 6 5 loc 4 gnd ttck gnd v cc 32 for more information www.linear.com/LTC5599 a pplica t ions i n f or m a t ion figure 14. evaluation board component side figure 15. evaluation board bottom side ltc 5599 5599f 33 for more information www.linear.com/LTC5599 a ppen d ix phase shift register (0x05) map this appendix summarizes the detailed value assignments for the phase shift register, including the extension bits and sign bit (bit 7 in register 0x00). table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph C240 C224 0 011100000 C239 C224 1 011100001 C238 C224 2 011100010 C237 C224 3 011100011 C236 C224 4 011100100 C235 C224 5 011100101 C234 C224 6 011100110 C233 C224 7 011100111 C232 C224 8 011101000 C231 C224 9 011101001 C230 C224 10 011101010 C229 C224 11 011101011 C228 C224 12 011101100 C227 C224 13 011101101 C226 C224 14 011101110 C225 C224 15 011101111 C224 C224 16 011110000 C223 C224 17 011110001 C222 C224 18 011110010 C221 C224 19 011110011 C220 C224 20 011110100 C219 C224 21 011110101 C218 C224 22 011110110 C217 C224 23 011110111 C216 C224 24 011111000 C215 C224 25 011111001 C214 C224 26 011111010 C213 C224 27 011111011 C212 C224 28 011111100 C211 C224 29 011111101 C210 C224 30 011111110 C209 C224 31 011111111 C208 C192 0 011000000 C207 C192 1 011000001 C206 C192 2 011000010 C205 C192 3 011000011 table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph C204 C192 4 011000100 C203 C192 5 011000101 C202 C192 6 011000110 C201 C192 7 011000111 C200 C192 8 011001000 C199 C192 9 011001001 C198 C192 10 011001010 C197 C192 11 011001011 C196 C192 12 011001100 C195 C192 13 011001101 C194 C192 14 011001110 C193 C192 15 011001111 C192 C192 16 011010000 C191 C192 17 011010001 C190 C192 18 011010010 C189 C192 19 011010011 C188 C192 20 011010100 C187 C192 21 011010101 C186 C192 22 011010110 C185 C192 23 011010111 C184 C192 24 011011000 C183 C192 25 011011001 C182 C192 26 011011010 C181 C192 27 011011011 C180 C192 28 011011100 C179 C192 29 011011101 C178 C192 30 011011110 C177 C192 31 011011111 C176 C160 0 010100000 C175 C160 1 010100001 C174 C160 2 010100010 C173 C160 3 010100011 C172 C160 4 010100100 C171 C160 5 010100101 C170 C160 6 010100110 C169 C160 7 010100111 C168 C160 8 010101000 C167 C160 9 010101001 C166 C160 10 010101010 C165 C160 11 010101011 C164 C160 12 010101100 (continued) ltc 5599 5599f 34 for more information www.linear.com/LTC5599 a ppen d ix table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph C163 C160 13 010101101 C162 C160 14 010101110 C161 C160 15 010101111 C160 C160 16 010110000 C159 C160 17 010110001 C158 C160 18 010110010 C157 C160 19 010110011 C156 C160 20 010110100 C155 C160 21 010110101 C154 C160 22 010110110 C153 C160 23 010110111 C152 C160 24 010111000 C151 C160 25 010111001 C150 C160 26 010111010 C149 C160 27 010111011 C148 C160 28 010111100 C147 C160 29 010111101 C146 C160 30 010111110 C145 C160 31 010111111 C144 C128 0 010000000 C143 C128 1 010000001 C142 C128 2 010000010 C141 C128 3 010000011 C140 C128 4 010000100 C139 C128 5 010000101 C138 C128 6 010000110 C137 C128 7 010000111 C136 C128 8 010001000 C135 C128 9 010001001 C134 C128 10 010001010 C133 C128 11 010001011 C132 C128 12 010001100 C131 C128 13 010001101 C130 C128 14 010001110 C129 C128 15 010001111 C128 C128 16 010010000 C127 C128 17 010010001 C126 C128 18 010010010 C125 C128 19 010010011 C124 C128 20 010010100 C123 C128 21 010010101 (continued) table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph C122 C128 22 010010110 C121 C128 23 010010111 C120 C128 24 010011000 C119 C128 25 010011001 C118 C128 26 010011010 C117 C128 27 010011011 C116 C128 28 010011100 C115 C128 29 010011101 C114 C128 30 010011110 C113 C128 31 010011111 C112 C96 0 001100000 C111 C96 1 001100001 C110 C96 2 001100010 C109 C96 3 001100011 C108 C96 4 001100100 C107 C96 5 001100101 C106 C96 6 001100110 C105 C96 7 001100111 C104 C96 8 001101000 C103 C96 9 001101001 C102 C96 10 001101010 C101 C96 11 001101011 C100 C96 12 001101100 C99 C96 13 001101101 C98 C96 14 001101110 C97 C96 15 001101111 C96 C96 16 001110000 C95 C96 17 001110001 C94 C96 18 001110010 C93 C96 19 001110011 C92 C96 20 001110100 C91 C96 21 001110101 C90 C96 22 001110110 C89 C96 23 001110111 C88 C96 24 001111000 C87 C96 25 001111001 C86 C96 26 001111010 C85 C96 27 001111011 C84 C96 28 001111100 C83 C96 29 001111101 C82 C96 30 001111110 (continued) ltc 5599 5599f 35 for more information www.linear.com/LTC5599 a ppen d ix table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph C81 C96 31 001111111 C80 C64 0 001000000 C79 C64 1 001000001 C78 C64 2 001000010 C77 C64 3 001000011 C76 C64 4 001000100 C75 C64 5 001000101 C74 C64 6 001000110 C73 C64 7 001000111 C72 C64 8 001001000 C71 C64 9 001001001 C70 C64 10 001001010 C69 C64 11 001001011 C68 C64 12 001001100 C67 C64 13 001001101 C66 C64 14 001001110 C65 C64 15 001001111 C64 C64 16 001010000 C63 C64 17 001010001 C62 C64 18 001010010 C61 C64 19 001010011 C60 C64 20 001010100 C59 C64 21 001010101 C58 C64 22 001010110 C57 C64 23 001010111 C56 C64 24 001011000 C55 C64 25 001011001 C54 C64 26 001011010 C53 C64 27 001011011 C52 C64 28 001011100 C51 C64 29 001011101 C50 C64 30 001011110 C49 C64 31 001011111 C48 C32 0 000100000 C47 C32 1 000100001 C46 C32 2 000100010 C45 C32 3 000100011 C44 C32 4 000100100 C43 C32 5 000100101 C42 C32 6 000100110 C41 C32 7 000100111 (continued) table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph C40 C32 8 000101000 C39 C32 9 000101001 C38 C32 10 000101010 C37 C32 11 000101011 C36 C32 12 000101100 C35 C32 13 000101101 C34 C32 14 000101110 C33 C32 15 000101111 C32 C32 16 000110000 C31 C32 17 000110001 C30 C32 18 000110010 C29 C32 19 000110011 C28 C32 20 000110100 C27 C32 21 000110101 C26 C32 22 000110110 C25 C32 23 000110111 C24 C32 24 000111000 C23 C32 25 000111001 C22 C32 26 000111010 C21 C32 27 000111011 C20 C32 28 000111100 C19 C32 29 000111101 C18 C32 30 000111110 C17 C32 31 000111111 C16 0 0 x00000000 C15 0 1 x00000001 C14 0 2 x00000010 C13 0 3 x00000011 C12 0 4 x00000100 C11 0 5 x00000101 C10 0 6 x00000110 C9 0 7 x00000111 C8 0 8 x00001000 C7 0 9 x00001001 C6 0 10 x00001010 C5 0 11 x00001011 C4 0 12 x00001100 C3 0 13 x00001101 C2 0 14 x00001110 C1 0 15 x00001111 0 0 16 x00010000 (continued) ltc 5599 5599f 36 for more information www.linear.com/LTC5599 a ppen d ix table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph 1 0 17 x00010001 2 0 18 x00010010 3 0 19 x00010011 4 0 20 x00010100 5 0 21 x00010101 6 0 22 x00010110 7 0 23 x00010111 8 0 24 x00011000 9 0 25 x00011001 10 0 26 x00011010 11 0 27 x00011011 12 0 28 x00011100 13 0 29 x00011101 14 0 30 x00011110 15 0 31 x00011111 16 32 0 100100000 17 32 1 100100001 18 32 2 100100010 19 32 3 100100011 20 32 4 100100100 21 32 5 100100101 22 32 6 100100110 23 32 7 100100111 24 32 8 100101000 25 32 9 100101001 26 32 10 100101010 27 32 11 100101011 28 32 12 100101100 29 32 13 100101101 30 32 14 100101110 31 32 15 100101111 32 32 16 100110000 33 32 17 100110001 34 32 18 100110010 35 32 19 100110011 36 32 20 100110100 37 32 21 100110101 38 32 22 100110110 39 32 23 100110111 40 32 24 100111000 41 32 25 100111001 (continued) table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph 42 32 26 100111010 43 32 27 100111011 44 32 28 100111100 45 32 29 100111101 46 32 30 100111110 47 32 31 100111111 48 64 0 101000000 49 64 1 101000001 50 64 2 101000010 51 64 3 101000011 52 64 4 101000100 53 64 5 101000101 54 64 6 101000110 55 64 7 101000111 56 64 8 101001000 57 64 9 101001001 58 64 10 101001010 59 64 11 101001011 60 64 12 101001100 61 64 13 101001101 62 64 14 101001110 63 64 15 101001111 64 64 16 101010000 65 64 17 101010001 66 64 18 101010010 67 64 19 101010011 68 64 20 101010100 69 64 21 101010101 70 64 22 101010110 71 64 23 101010111 72 64 24 101011000 73 64 25 101011001 74 64 26 101011010 75 64 27 101011011 76 64 28 101011100 77 64 29 101011101 78 64 30 101011110 79 64 31 101011111 80 96 0 101100000 81 96 1 101100001 82 96 2 101100010 (continued) ltc 5599 5599f 37 for more information www.linear.com/LTC5599 a ppen d ix table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph 83 96 3 101100011 84 96 4 101100100 85 96 5 101100101 86 96 6 101100110 87 96 7 101100111 88 96 8 101101000 89 96 9 101101001 90 96 10 101101010 91 96 11 101101011 92 96 12 101101100 93 96 13 101101101 94 96 14 101101110 95 96 15 101101111 96 96 16 101110000 97 96 17 101110001 98 96 18 101110010 99 96 19 101110011 100 96 20 101110100 101 96 21 101110101 102 96 22 101110110 103 96 23 101110111 104 96 24 101111000 105 96 25 101111001 106 96 26 101111010 107 96 27 101111011 108 96 28 101111100 109 96 29 101111101 110 96 30 101111110 111 96 31 101111111 112 128 0 110000000 113 128 1 110000001 114 128 2 110000010 115 128 3 110000011 116 128 4 110000100 117 128 5 110000101 118 128 6 110000110 119 128 7 110000111 120 128 8 110001000 121 128 9 110001001 122 128 10 110001010 123 128 11 110001011 table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph 124 128 12 110001100 125 128 13 110001101 126 128 14 110001110 127 128 15 110001111 128 128 16 110010000 129 128 17 110010001 130 128 18 110010010 131 128 19 110010011 132 128 20 110010100 133 128 21 110010101 134 128 22 110010110 135 128 23 110010111 136 128 24 110011000 137 128 25 110011001 138 128 26 110011010 139 128 27 110011011 140 128 28 110011100 141 128 29 110011101 142 128 30 110011110 143 128 31 110011111 144 160 0 110100000 145 160 1 110100001 146 160 2 110100010 147 160 3 110100011 148 160 4 110100100 149 160 5 110100101 150 160 6 110100110 151 160 7 110100111 152 160 8 110101000 153 160 9 110101001 154 160 10 110101010 155 160 11 110101011 156 160 12 110101100 157 160 13 110101101 158 160 14 110101110 159 160 15 110101111 160 160 16 110110000 161 160 17 110110001 162 160 18 110110010 163 160 19 110110011 164 160 20 110110100 (continued) (continued) ltc 5599 5599f 38 for more information www.linear.com/LTC5599 a ppen d ix table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph 165 160 21 110110101 166 160 22 110110110 167 160 23 110110111 168 160 24 110111000 169 160 25 110111001 170 160 26 110111010 171 160 27 110111011 172 160 28 110111100 173 160 29 110111101 174 160 30 110111110 175 160 31 110111111 176 192 0 111000000 177 192 1 111000001 178 192 2 111000010 179 192 3 111000011 180 192 4 111000100 181 192 5 111000101 182 192 6 111000110 183 192 7 111000111 184 192 8 111001000 185 192 9 111001001 186 192 10 111001010 187 192 11 111001011 188 192 12 111001100 189 192 13 111001101 190 192 14 111001110 191 192 15 111001111 192 192 16 111010000 193 192 17 111010001 194 192 18 111010010 195 192 19 111010011 196 192 20 111000100 197 192 21 111010101 198 192 22 111010110 199 192 23 111010111 200 192 24 111011000 201 192 25 111011001 202 192 26 111011010 203 192 27 111011011 204 192 28 111011100 (continued) table 9. register 0x05 phase shift register settings, including the extension bits and sign bit ( bit 7 in register 0 x 00) m ph n coarse n ph b ph 205 192 29 111011101 206 192 30 111011110 207 192 31 111011111 208 224 0 111100000 209 224 1 111100001 210 224 2 111100010 211 224 3 111100011 212 224 4 111100100 213 224 5 111100101 214 224 6 111100110 215 224 7 111100111 216 224 8 111101000 217 224 9 111101001 218 224 10 111101010 219 224 11 111101011 220 224 12 111101100 221 224 13 111101101 222 224 14 111101110 223 224 15 111101111 224 224 16 111110000 225 224 17 111110001 226 224 18 111110010 227 224 19 111110011 228 224 20 111110100 229 224 21 111110101 230 224 22 111110110 231 224 23 111110111 232 224 24 111111000 233 224 25 111111001 234 224 26 111111010 235 224 27 111111011 236 224 28 111111100 237 224 29 111111101 238 224 30 111111110 239 224 31 111111111 (continued) ltc 5599 5599f 39 for more information www.linear.com/LTC5599 appen d ix table 10. serial port register contents addr msb [6] [5] [4] [3] [2] [1] lsb r/w default 0x00 iqphsign freq[6] freq[5] freq[4] freq[3] freq[2] freq[1] freq[0] r/w 0x2e 0x01 tempupdt agctrl qdisable gain[4] gain[3] gain[2] gain[1] gain[0] r/w 0x84 0x02 offseti[7] offseti[6] offseti[5] offseti[4] offseti[3] offseti[2] offseti[1] offseti[0] r/w 0x80 0x03 offsetq[7] offsetq[6] offsetq[5] offsetq[4] offsetq[3] offsetq[2] offsetq[1] offsetq[0] r/w 0x80 0x04 iqgr[7] iqgr[6] iqgr[5] iqgr[4] iqgr[3] iqgr[2] iqgr[1] iqgr[0] r/w 0x80 0x05 iqphe[2] iqphe[1] iqphe[0] iqphf[4] iqphf[3] iqphf[2] iqphf[1] iqphf[0] r/w 0x10 0x06 * * * cloen cloo[3] cloo[2] cloo[1] cloo[0] r/w 0x50 0x07 0 ? 0 ? 0 ? 0 ? gainf[3] gainf[2] gainf[1] gainf[0] r/w 0x06 0x08 0 ? 0 ? 0 ? 0 ? sreset tempcorr therminp * r/w 0x00 0x09 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? r 0x00 0x0a chipid[7] chipid[6] chipid[5] chipid[4] chipid[3] chipid[2] chipid[1] chipid[0] r 0x01 0x0b 0 ? 0 ? 0 ? 0 ? fuse[3] fuse[2] fuse[1] fuse[0] r 0x0x 0x0c 0 ? 0 ? cppp0[5] cppp0[4] cppp0[3] cppp0[2] cppp0[1] cppp0[0] r 0xxx 0x0d 0 ? cppp1[6] cppp1[5] cppp1[4] cppp1[3] cppp1[2] cppp1[1] cppp1[0] r 0x0x 0x0e 0 ? 0 ? cppm0[5] cppm0[4] cppm0[3] cppm0[2] cppm0[1] cppm0[0] r 0xxx 0x0f 0 ? cppm1[6] cppm1[5] cppm1[4] cppm1[3] cppm1[2] cppm1[1] cppm1[0] r 0x0x 0x10 0 ? gpi0[6] gpi0[5] gpi0[4] gpi0[3] gpi0[2] gpi0[1] gpi0[0] r 0x08 0x11 gpi1[7] gpi1[6] gpi1[5] gpi1[4] gpi1[3] gpi1[2] gpi1[1] gpi1[0] r 0xff 0x12 0 ? gpi2[6] gpi2[5] gpi2[4] gpi2[3] gpi2[2] gpi2[1] gpi2[0] r 0x01 0x13 0 ? gmi0[6] gmi0[5] gmi0[4] gmi0[3] gmi0[2] gmi0[1] gmi0[0] r 0x08 0x14 gmi1[7] gmi1[6] gmi1[5] gmi1[4] gmi1[3] gmi1[2] gmi1[1] gmi1[0] r 0xff 0x15 0 ? gmi2[6] gmi2[5] gmi2[4] gmi2[3] gmi2[2] gmi2[1] gmi2[0] r 0x01 0x16 0 ? gpq0[6] gpq0[5] gpq0[4] gpq0[3] gpq0[2] gpq0[1] gpq0[0] r 0x08 0x17 gpq1[7] gpq1[6] gpq1[5] gpq1[4] gpq1[3] gpq1[2] gpq1[1] gpq1[0] r 0xff 0x18 0 ? gpq2[6] gpq2[5] gpq2[4] gpq2[3] gpq2[2] gpq2[1] gpq2[0] r 0x01 0x19 0 ? gmq0[6] gmq0[5] gmq0[4] gmq0[3] gmq0[2] gmq0[1] gmq0[0] r 0x08 0x1a gmq1[7] gmq1[6] gmq1[5] gmq1[4] gmq1[3] gmq1[2] gmq1[1] gmq1[0] r 0xff 0x1b 0 ? gmq2[6] gmq2[5] gmq2[4] gmq2[3] gmq2[2] gmq2[1] gmq2[0] r 0x01 0x1c 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? r 0x00 0x1d 0 ? 0 ? 0 ? 0 ? clo[3] clo[2] clo[1] clo[0] r 0x00 0x1e 0 ? 0 ? 0 ? gor idt[3] idt[2] idt[1] idt[0] r 0x04 0x1f 0 ? 0 ? 0 ? 0 ? temp[3] temp[2] temp[1] temp[0] r 0x0y *unused ? read-only; values written are disregarded, x = production dependent, y = resets to 7 after en from low to high with tempupdt = 1, for en = low all read-only (r) registers default to 0x00. ltc 5599 5599f 40 for more information www.linear.com/LTC5599 appen d ix table 11. serial port register bit field summary bits function description valid values default agctrl analog gain control enable enables analog control through v ctrl (pin 1) when agctrl = 1. 0, 1 1 chipid[7:0] chip id 1 1 clo[3:0] lo port match cap array lo port match, automatically adjusted through programming freq[6:0] 0x00 to 0x0f 0x00 cloo[3:0] lo port cap array override programs lo port match capacitor array when cloen = 0 0x00 to 0x0f 0x00 cloen automatic lo match enable automatic lo port impedance matching enabled when cloen = 1. override bits cloo[3:0] control lo port match when cloen = 0. 0, 1 1 cppm0[5:0] c ppq fine control c ppq = cppm0[5:0] + number of 1s in cppm1[6:0] 64 0x00 to 0x5f 0xxx cppm1[6:0] c ppq coarse control 0x00 to 0x7f 0x0x cppp0[5:0] c ppi fine control c ppi = cppp0[5:0] + number of 1s in cppp1[6:0] 64 0x00 to 0x5f 0xxx cppp1[6:0] c ppi coarse control 0x00 to 0x7f 0x0x freq[6:0] poly-phase filter frequency programs the center frequency of the poly- phase filter, according to table 5. 0x00 to 0x79 0x2e fuse[3:0] fuse read out 0x00 to 0x0f 0x0x gain[4:0] coarse digital gain control programs the conversion gain in 1db steps, according to table 3. 0x00 to 0x13 0x04 gainf[3:0] fine digital gain control conversion gain control in approximately 0.1 db steps, when tempcorr = 1. 0x00 to 0x0f 0x00 gmi0[6:0] fine gmi dac read-out bbmi input stage gain gmi. 0x00 to 0x7f 0x08 gmi1[7:0] coarse gmi dac read-out1 gmi = gmi0[6:0] + (number of 1s in gmi1[7:0] and gmi2[6:0]) 128 0x00 to 0x07 0xff gmi2[6:0] coarse gmi dac read-out2 0x00 to 0x07 0x01 gmq0[6:0] fine gmq dac read-out bbmq input stage gain gmq. 0x00 to 0x7f 0x08 gmq1[7:0] coarse gmq dac read-out1 gmq = gmq0[6:0] + (number of 1s in gmq1[7:0] and gmq2[6:0]) 128 0x00 to 0x07 0xff gmq2[6:0] coarse gmq dac read-out2 0x00 to 0x07 0x01 gor gain out of range for dg < C19 gor = 1; else gor = 0 0, 1 0 gpi0[6:0] fine gpi dac read-out bbpi input stage gain gpi. 0x00 to 0x7f 0x08 gpi1[7:0] coarse gpi dac read-out1 gpi = gpi0[6:0] + (number of 1s in gpi1[7:0] and gpi2[6:0]) 128 0x00 to 0x07 0xff gpi2[6:0] coarse gpi dac read-out2 0x00 to 0x07 0x01 gpq0[6:0] fine gpq dac read-out bbpq input stage gain gpq. 0x00 to 0x7f 0x08 gpq1[7:0] coarse gpq dac read-out1 gpq = gpq0[6:0] + (number of 1s in gpq1[7:0] and gpq2[6:0]) 128 0x00 to 0x 07 0xff gpq2[6:0] coarse gpq dac read-out2 0x00 to 0x07 0x01 idt[3:0] rf buffer bias 0x00 to 0x0d 0x04 iqgr[7:0] i/q gain ratio control adjust the gain difference in approximate constant steps in db. see table 4. 0x00 to 0xff 0x80 iqphe[2:0] i/q phase extension bits extend the iq phase adjustment range. see table 9. 0x00 to 0x07 0x00 iqphf[4:0] fine i/q phase balance control fine adjustment of iq lo phase difference. see table 9. zero phase shift for 0x10. 0x00 to 0x1f 0x10 iqphsign sign iq phase extension bits encodes the sign of the iq phase extension bits iqphe[2:0]. positive for iqphsign = 1. 0, 1 0 offseti[7:0] i-channel offset control adjusts dc offset in the i-channel. zero offset for 0x80. see page 19. 0x01 to 0xff 0x80 offsetq[7:0] q-channel offset control adjusts dc offset in the q-channel. zero offset for 0x80. see page 19. 0x01 to 0xff 0x80 qdisable disable q-channel qdisable = 1 shuts down the q-channel, turning the LTC5599 into an upconversion mixer. 0, 1 0 sreset soft reset writing 1 to this bit resets all registers to their default values. 0, 1 0 temp[3:0] thermometer output digital representation of die temperature. step size about 10c. 0x00 to 0x07 0x07 tempcorr temperature correction disable tempcorr = 1 disables temperature correction of the gain, and enables manual fine-adjustment using bits gainf[3:0]. 0, 1 0 tempupdt t emperature correction update tempupdt = 1 synchronizes temperature correction of the gain to a low - high transition on the ttck pin. asynchronous correction for tempupdt = 0. 0, 1 1 therminp thermometer input select for test purposes only. should be set to 0. 0 0 ltc 5599 5599f 41 for more information www.linear.com/LTC5599 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 rev b recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b) ltc 5599 5599f 42 for more information www.linear.com/LTC5599 ? linear technology corporation 2014 lt 0814 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC5599 r ela t e d p ar t s typical a pplica t ion LTC5599 v cc 3.3v 5599 ta01a 1nf + 4.7f 90 0 i-channel q-channel thermometer ttck spi baseband generator en 8 9 1 23 10 11 3 4 6 16 2, 5, 12 22, 21, 20, 19 24 rf = 90mhz to 1300mhz pa vco/synthesizer 10nf 13, 14, 15, 17, 18 v ctrl i-dac q-dac v i v i part number description comments infrastructure lt5518 1.5ghz to 2.4ghz high linearity direct quadrature modulator 22.8dbm oip3 at 2ghz, C158.2dbm/hz noise floor, 3k 2.1v dc baseband interface, 5v/128ma supply lt5528 1.5ghz to 2.4ghz high linearity direct quadrature modulator 21.8dbm oip3 at 2ghz, C159.3dbm/hz noise floor, 50 0.5v dc baseband interface, 5v/128ma supply lt5558 600mhz to 1100mhz high linearity direct quadrature modulator 22.4dbm oip3 at 900mhz, C158dbm/hz noise floor, 3k 2.1v dc baseband interface, 5v/108ma supply lt5568 700mhz to 1050mhz high linearity direct quadrature modulator 22.9dbm oip3 at 850mhz, C160.3dbm/hz noise floor, 50 0.5v dc baseband interface, 5v/117ma supply lt5571 620mhz to 1100mhz high linearity direct quadrature modulator 21.7dbm oip3 at 900mhz, C159dbm/hz noise floor, hi-z 0.5v dc baseband interface, 5v/97ma supply lt5572 1.5ghz to 2.5ghz high linearity direct quadrature modulator 21.6dbm oip3 at 2ghz, C158.6dbm/hz noise floor, hi-z 0.5v dc baseband interface, 5v/120ma supply ltc5598 5 mhz to 1600mhz high linearity direct quadrature modulator 27.7dbm oip3 at 140mhz, C160dbm/ hz noise floor with p out = 5dbm lt5560 0.01mhz to 4 ghz low power active mixer iip3 = 9dbm, 2.6db conversion gain, 9.3db nf, 3.0v/10ma supply current lt5506/5546 40mhz to 500mhz quadrature demodulator with vga 56db gain , C49 to 0dbm iip3, 6.8db nf, 1.8v to 5.25v/26.5ma supply current ltc5510 1mhz to 6ghz, 3.3v wideband high linearity active mixer 1.5db gain, 27dbm iip3, 11.6db nf, 3.3v/105ma supply current rf power detector lt5581 6ghz low power rms detector 40db dynamic range, 1db accuracy over t emperature, 1.5ma supply current ltc5582 40mhz to 10ghz rms power detector 57db dynamic range, 1db accuracy over temperature, single - ended rf input (no transformer) lt5534 50mhz to 3ghz rf power detector with 60db dynamic range 60db dynamic range, linear-in-db response, 2.7v to 5.25v/7ma lt5537 lf to 1ghz wide dynamic range rf/if log detector 83db dynamic range, linear-in-db response, 2.7v to 5.25v/13.5ma figure 16. 90mhz to 1300mhz direct conversion transmitter application ltc 5599 5599f 39nh 15pf |
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